iCE40/yosys - [no description]

	Commit message (Expand)	Author	Age	Files	Lines
*	Major redesign of expr width/sign detecion (verilog/ast frontend)	Clifford Wolf	2013-07-09	1	-1/+1
*	Added defparam support to Verilog/AST frontend	Clifford Wolf	2013-07-04	2	-10/+41
*	More fixes for bugs found using xsthammer	Clifford Wolf	2013-06-13	2	-4/+14
*	Further improved and extended xsthammer	Clifford Wolf	2013-06-11	1	-0/+1
*	Enabled AST/Verilog front-end optimizations per default	Clifford Wolf	2013-06-10	1	-1/+10
*	Added SAT generator and simple sat_solve command	Clifford Wolf	2013-06-07	2	-3/+4
*	added option '-Dname[=definition]' to command 'read_verilog'	Johann Glaser	2013-05-19	3	-4/+19
*	Added support for verilog === operator	Clifford Wolf	2013-05-07	1	-0/+2
*	Added AST_INITIAL (before verilog "initial" was mapped to AST_ALWAYS)	Clifford Wolf	2013-03-31	1	-1/+1
*	Implemented proper handling of stub placeholder modules	Clifford Wolf	2013-03-28	1	-1/+9
*	Improvements and bugfixes for generate blocks with local signals	Clifford Wolf	2013-03-26	1	-1/+1
*	Added mem2reg option to verilog frontend	Clifford Wolf	2013-03-24	1	-1/+11
*	Tiny fixes to verilog parser	Clifford Wolf	2013-03-23	1	-1/+6
*	Added help messages to ilang and verilog frontends	Clifford Wolf	2013-03-01	1	-1/+46
*	Moved stand-alone libs to libs/ directory and added libs/subcircuit	Clifford Wolf	2013-02-27	1	-1/+1
*	Added support for verilog genblock[index].member syntax	Clifford Wolf	2013-02-26	1	-10/+16
*	Added support for "always @(*)"	Clifford Wolf	2013-01-16	1	-0/+3
*	added .gitignore files	Clifford Wolf	2013-01-05	1	-0/+4
*	initial import	Clifford Wolf	2013-01-05	7	-0/+2124