iCE40/yosys - [no description]

	Commit message (Expand)	Author	Age	Files	Lines
*	Bugfix in verilog_defaults argument parser	Clifford Wolf	2017-12-24	1	-1/+1
*	Add Verilog "automatic" keyword (ignored in synthesis)	Clifford Wolf	2017-11-23	2	-13/+18
*	Accept real-valued delay values	Clifford Wolf	2017-11-18	1	-0/+1
*	Accommodate Windows-style paths during include-file processing.	William D. Jones	2017-11-14	1	-4/+20
*	Resolved classical Bison IF/THEN/ELSE shift/reduce conflict using the textboo...	Udi Finkelstein	2017-09-30	1	-3/+5
*	Minor coding style fix	Clifford Wolf	2017-09-26	1	-1/+1
*	Merge branch 'master' of https://github.com/combinatorylogic/yosys into combi...	Clifford Wolf	2017-09-26	1	-41/+69
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\| *	Adding support for string macros and macros with arguments after include	combinatorylogic	2017-09-21	1	-41/+69
* \|	Fix ignoring of simulation timings so that invalid module parameters cause sy...	Clifford Wolf	2017-09-26	2	-4/+2
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*	Add a paragraph about pre-defined macros to read_verilog help message	Clifford Wolf	2017-07-21	1	-0/+4
*	Fix generation of vlogtb output in yosys-smtbmc for "rand reg" and "rand cons...	Clifford Wolf	2017-06-07	1	-0/+1
*	Fix handling of Verilog ~& and ~\| operators	Clifford Wolf	2017-06-01	1	-0/+8
*	Add support for localparam in module header	Clifford Wolf	2017-04-30	1	-1/+7
*	Add support for `resetall compiler directive	Clifford Wolf	2017-04-26	1	-0/+7
*	Fix verilog pre-processor for multi-level relative includes	Clifford Wolf	2017-03-14	1	-4/+26
*	Allow $anyconst, etc. in non-formal SV mode	Clifford Wolf	2017-03-01	1	-1/+1
*	Add $live and $fair cell types, add support for s_eventually keyword	Clifford Wolf	2017-02-25	2	-1/+28
*	Add support for SystemVerilog unique, unique0, and priority case	Clifford Wolf	2017-02-23	2	-4/+25
*	Added SystemVerilog support for ++ and --	Clifford Wolf	2017-02-23	2	-1/+12
*	Add checker support to verilog front-end	Clifford Wolf	2017-02-09	2	-11/+24
*	Add SV "rand" and "const rand" support	Clifford Wolf	2017-02-08	2	-8/+28
*	Further improve cover() support	Clifford Wolf	2017-02-04	1	-0/+6
*	Add $cover cell type and SVA cover() support	Clifford Wolf	2017-02-04	2	-1/+8
*	Add "enum" and "typedef" lexer support	Clifford Wolf	2017-01-17	2	-1/+4
*	Added "verilog_defines" command	Clifford Wolf	2016-12-15	1	-0/+60
*	Added support for macros as include file names	Clifford Wolf	2016-11-28	1	-0/+2
*	Bugfix in "read_verilog -D NAME=VAL" handling	Clifford Wolf	2016-11-28	1	-3/+3
*	Added support for hierarchical defparams	Clifford Wolf	2016-11-15	1	-3/+2
*	Remember global declarations and defines accross read_verilog calls	Clifford Wolf	2016-11-15	3	-3/+17
*	Added $anyseq cell type	Clifford Wolf	2016-10-14	1	-1/+1
*	Removed $aconst cell type	Clifford Wolf	2016-08-30	1	-1/+1
*	Removed $predict again	Clifford Wolf	2016-08-28	2	-8/+1
*	Added read_verilog -norestrict -assume-asserts	Clifford Wolf	2016-08-26	4	-5/+40
*	Improved verilog parser errors	Clifford Wolf	2016-08-25	1	-0/+3
*	Added SV "restrict" keyword	Clifford Wolf	2016-08-24	1	-1/+2
*	Fixed bug in parsing real constants	Clifford Wolf	2016-08-06	1	-4/+4
*	Added $anyconst and $aconst	Clifford Wolf	2016-07-27	1	-1/+1
*	Added "read_verilog -dump_rtlil"	Clifford Wolf	2016-07-27	1	-1/+9
*	Fixed a verilog parser memory leak	Clifford Wolf	2016-07-25	1	-0/+1
*	Fixed parsing of empty positional cell ports	Clifford Wolf	2016-07-25	1	-2/+31
*	No tristate warning message for "read_verilog -lib"	Clifford Wolf	2016-07-23	3	-8/+11
*	Added $initstate cell type and vlog function	Clifford Wolf	2016-07-21	1	-0/+2
*	After reading the SV spec, using non-standard predict() instead of expect()	Clifford Wolf	2016-07-21	2	-6/+10
*	Added basic support for $expect cells	Clifford Wolf	2016-07-13	2	-1/+9
*	Allow defining input ports as "input logic" in SystemVerilog	Ruben Undheim	2016-06-20	1	-2/+2
*	Added support for SystemVerilog packages with localparam definitions	Ruben Undheim	2016-06-18	2	-0/+33
*	Small improvements in Verilog front-end docs	Clifford Wolf	2016-05-20	1	-0/+3
*	Added "yosys -D" feature	Clifford Wolf	2016-04-21	1	-1/+1
*	Fixed handling of parameters and const functions in casex/casez pattern	Clifford Wolf	2016-04-21	1	-2/+6
*	Fixed Verilog parser fix and more similar improvements	Clifford Wolf	2016-03-15	1	-18/+9