aboutsummaryrefslogtreecommitdiffstats
path: root/frontends/verilog
Commit message (Expand)AuthorAgeFilesLines
* Fix verilog pre-processor for multi-level relative includesClifford Wolf2017-03-141-4/+26
* Allow $anyconst, etc. in non-formal SV modeClifford Wolf2017-03-011-1/+1
* Add $live and $fair cell types, add support for s_eventually keywordClifford Wolf2017-02-252-1/+28
* Add support for SystemVerilog unique, unique0, and priority caseClifford Wolf2017-02-232-4/+25
* Added SystemVerilog support for ++ and --Clifford Wolf2017-02-232-1/+12
* Add checker support to verilog front-endClifford Wolf2017-02-092-11/+24
* Add SV "rand" and "const rand" supportClifford Wolf2017-02-082-8/+28
* Further improve cover() supportClifford Wolf2017-02-041-0/+6
* Add $cover cell type and SVA cover() supportClifford Wolf2017-02-042-1/+8
* Add "enum" and "typedef" lexer supportClifford Wolf2017-01-172-1/+4
* Added "verilog_defines" commandClifford Wolf2016-12-151-0/+60
* Added support for macros as include file namesClifford Wolf2016-11-281-0/+2
* Bugfix in "read_verilog -D NAME=VAL" handlingClifford Wolf2016-11-281-3/+3
* Added support for hierarchical defparamsClifford Wolf2016-11-151-3/+2
* Remember global declarations and defines accross read_verilog callsClifford Wolf2016-11-153-3/+17
* Added $anyseq cell typeClifford Wolf2016-10-141-1/+1
* Removed $aconst cell typeClifford Wolf2016-08-301-1/+1
* Removed $predict againClifford Wolf2016-08-282-8/+1
* Added read_verilog -norestrict -assume-assertsClifford Wolf2016-08-264-5/+40
* Improved verilog parser errorsClifford Wolf2016-08-251-0/+3
* Added SV "restrict" keywordClifford Wolf2016-08-241-1/+2
* Fixed bug in parsing real constantsClifford Wolf2016-08-061-4/+4
* Added $anyconst and $aconstClifford Wolf2016-07-271-1/+1
* Added "read_verilog -dump_rtlil"Clifford Wolf2016-07-271-1/+9
* Fixed a verilog parser memory leakClifford Wolf2016-07-251-0/+1
* Fixed parsing of empty positional cell portsClifford Wolf2016-07-251-2/+31
* No tristate warning message for "read_verilog -lib"Clifford Wolf2016-07-233-8/+11
* Added $initstate cell type and vlog functionClifford Wolf2016-07-211-0/+2
* After reading the SV spec, using non-standard predict() instead of expect()Clifford Wolf2016-07-212-6/+10
* Added basic support for $expect cellsClifford Wolf2016-07-132-1/+9
* Allow defining input ports as "input logic" in SystemVerilogRuben Undheim2016-06-201-2/+2
* Added support for SystemVerilog packages with localparam definitionsRuben Undheim2016-06-182-0/+33
* Small improvements in Verilog front-end docsClifford Wolf2016-05-201-0/+3
* Added "yosys -D" featureClifford Wolf2016-04-211-1/+1
* Fixed handling of parameters and const functions in casex/casez patternClifford Wolf2016-04-211-2/+6
* Fixed Verilog parser fix and more similar improvementsClifford Wolf2016-03-151-18/+9
* Use left-recursive rule for cell_port_list in Verilog parser.Andrew Becker2016-03-151-6/+10
* Fixed typos in verilog_defaults help messageClifford Wolf2016-03-101-3/+3
* Fixed handling of parameters and localparams in functionsClifford Wolf2015-11-111-1/+1
* Fixed bug in verilog parserClifford Wolf2015-10-151-1/+1
* SystemVerilog also has assume(), added implicit -D FORMALClifford Wolf2015-10-133-4/+5
* Added support for "parameter" and "localparam" in global contextClifford Wolf2015-10-071-0/+2
* Added read_verilog -nodpiClifford Wolf2015-09-231-0/+19
* Fixed support for $write system taskClifford Wolf2015-09-231-1/+1
* Fixed detection of "task foo(bar);" syntax errorClifford Wolf2015-09-221-0/+2
* Fixed segfault on invalid verilog constant 1'b_Clifford Wolf2015-09-221-1/+1
* Small corrections to const2ast warning messagesClifford Wolf2015-08-171-2/+2
* Check base-n literals only contain valid digitsFlorian Zeitz2015-08-171-0/+3
* Warn on literals exceeding the specified bit widthFlorian Zeitz2015-08-171-34/+39
* Another block of spelling fixesLarry Doolittle2015-08-142-3/+3
generated by cgit v1.2.3 (git 2.25.1) at 2024-10-06 01:21:02 +0000