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* Merge pull request #1775 from huaixv/asserts_locationsN. Engelhardt2020-03-191-7/+30
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| * Add precise locations for assertshuaixv2020-03-191-7/+30
* | Add AST node source location information in a couple more parser rules.Alberto Gonzalez2020-03-171-0/+2
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* Merge pull request #1759 from zeldin/constant_with_comment_reduxMiodrag Milanović2020-03-141-11/+20
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| * refixed parsing of constant with comment between size and valueMarcus Comstedt2020-03-111-11/+20
* | verilog: also set location for simple_behavioral_stmtEddie Hung2020-03-101-0/+4
* | Set AST source locations in more parser rules.Alberto Gonzalez2020-03-101-2/+49
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* Fix partsel expr bit width handling and add test caseClaire Wolf2020-03-081-4/+6
* Fix bison warning for "pure-parser" optionClaire Wolf2020-03-031-1/+1
* Closes #1717. Add more precise Verilog source location information to AST and...Alberto Gonzalez2020-02-231-11/+77
* Merge pull request #1703 from YosysHQ/eddie/specify_improveEddie Hung2020-02-211-28/+80
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| * verilog: add support for more delays than just rise/fallEddie Hung2020-02-191-1/+40
| * verilog: ignore ranges too without -specifyEddie Hung2020-02-131-1/+2
| * verilog: improve specify support when not in -specify modeEddie Hung2020-02-131-13/+7
| * verilog: ignore '&&&' when not in -specify modeEddie Hung2020-02-131-4/+5
| * specify: system timing checks to accept min:typ:max tripleEddie Hung2020-02-131-12/+29
* | Merge pull request #1642 from jjj11x/jjj11x/sv-enumClaire Wolf2020-02-201-2/+104
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| * add attributes for enumerated values in ilangJeff Wang2020-02-171-1/+8
| * lexer doesn't seem to return TOK_REG for logic anymoreJeff Wang2020-01-161-3/+4
| * allow enum typedefsJeff Wang2020-01-161-1/+6
| * partial rebase of PeterCrozier's enum work onto current masterJeff Wang2020-01-161-1/+90
* | Merge pull request #1679 from thasti/delay-parsingN. Engelhardt2020-02-131-2/+2
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| * | correct wire declaration grammar for #1614Stefan Biereigel2020-02-031-2/+2
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* | sv: Improve handling of wildcard port connectionsDavid Shah2020-02-021-3/+5
* | hierarchy: Resolve SV wildcard port connectionsDavid Shah2020-02-021-1/+1
* | sv: Add lexing and parsing of .* (wildcard port conns)David Shah2020-02-021-1/+4
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* kernel: require \B_SIGNED=0 on $shl, $sshl, $shr, $sshr.whitequark2019-12-041-5/+5
* sv: Correct parsing of always_comb, always_ff and always_latchDavid Shah2019-11-211-2/+37
* Use "(id)" instead of "id" for types as temporary hackClifford Wolf2019-10-141-11/+69
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| * sv: Disambiguate interface portsDavid Shah2019-10-031-3/+19
| * sv: Fix memories of typedefsDavid Shah2019-10-031-1/+1
| * sv: Add %expectDavid Shah2019-10-031-0/+1
| * sv: Add support for memory typedefsDavid Shah2019-10-031-1/+19
| * sv: Fix typedef parametersDavid Shah2019-10-031-4/+17
| * sv: Switch parser to glr, prep for typedefDavid Shah2019-10-031-4/+34
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* substr() -> compare()Eddie Hung2019-08-071-4/+4
* Some cleanups in "ignore specify parser"Clifford Wolf2019-07-031-79/+5
* Improve specify dummy parser, fixes #1144Clifford Wolf2019-06-281-2/+9
* Make genvar a signed typeEddie Hung2019-06-201-0/+1
* Merge branch 'unpacked_arrays' of https://github.com/towoe/yosys-sv into towo...Clifford Wolf2019-06-201-1/+7
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| * Unpacked array declaration using sizeTobias Wölfel2019-06-191-1/+7
* | Add "read_verilog -pwires" feature, closes #1106Clifford Wolf2019-06-191-2/+6
* | Add defaultvalue attributeClifford Wolf2019-06-191-0/+11
* | Fix handling of "logic" variables with initial valueClifford Wolf2019-06-191-2/+2
* | Fixed brojen $error()/$info/$warning() on non-generate blocksUdi Finkelstein2019-06-111-2/+12
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* Merge branch 'pr_elab_sys_tasks' of https://github.com/udif/yosys into cliffo...Clifford Wolf2019-06-071-1/+10
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| * Initial implementation of elaboration system tasksUdi Finkelstein2019-05-031-1/+10
* | Cleanup tux3-implicit_named_connectionClifford Wolf2019-06-071-1/+1
* | Merge branch 'implicit_named_connection' of https://github.com/tux3/yosys int...Clifford Wolf2019-06-071-1/+10
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| * | SystemVerilog support for implicit named port connectionstux32019-06-061-9/+17
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