aboutsummaryrefslogtreecommitdiffstats
path: root/frontends/verilog/verilog_parser.y
Commit message (Expand)AuthorAgeFilesLines
* Use "(id)" instead of "id" for types as temporary hackClifford Wolf2019-10-141-11/+69
|\
| * sv: Disambiguate interface portsDavid Shah2019-10-031-3/+19
| * sv: Fix memories of typedefsDavid Shah2019-10-031-1/+1
| * sv: Add %expectDavid Shah2019-10-031-0/+1
| * sv: Add support for memory typedefsDavid Shah2019-10-031-1/+19
| * sv: Fix typedef parametersDavid Shah2019-10-031-4/+17
| * sv: Switch parser to glr, prep for typedefDavid Shah2019-10-031-4/+34
|/
* substr() -> compare()Eddie Hung2019-08-071-4/+4
* Some cleanups in "ignore specify parser"Clifford Wolf2019-07-031-79/+5
* Improve specify dummy parser, fixes #1144Clifford Wolf2019-06-281-2/+9
* Make genvar a signed typeEddie Hung2019-06-201-0/+1
* Merge branch 'unpacked_arrays' of https://github.com/towoe/yosys-sv into towo...Clifford Wolf2019-06-201-1/+7
|\
| * Unpacked array declaration using sizeTobias Wölfel2019-06-191-1/+7
* | Add "read_verilog -pwires" feature, closes #1106Clifford Wolf2019-06-191-2/+6
* | Add defaultvalue attributeClifford Wolf2019-06-191-0/+11
* | Fix handling of "logic" variables with initial valueClifford Wolf2019-06-191-2/+2
* | Fixed brojen $error()/$info/$warning() on non-generate blocksUdi Finkelstein2019-06-111-2/+12
|/
* Merge branch 'pr_elab_sys_tasks' of https://github.com/udif/yosys into cliffo...Clifford Wolf2019-06-071-1/+10
|\
| * Initial implementation of elaboration system tasksUdi Finkelstein2019-05-031-1/+10
* | Cleanup tux3-implicit_named_connectionClifford Wolf2019-06-071-1/+1
* | Merge branch 'implicit_named_connection' of https://github.com/tux3/yosys int...Clifford Wolf2019-06-071-1/+10
|\ \
| * | SystemVerilog support for implicit named port connectionstux32019-06-061-9/+17
* | | Fixed memory leak.Maciej Kurc2019-06-051-0/+4
* | | Added support for parsing attributes on port connections.Maciej Kurc2019-05-311-10/+10
|/ /
* | fix indentation across filesStefan Biereigel2019-05-231-2/+2
* | make lexer/parser aware of wand/wor net typesStefan Biereigel2019-05-231-1/+7
* | Merge pull request #1013 from antmicro/parameter_attributesClifford Wolf2019-05-161-2/+2
|\ \
| * | Added support for parsing attributes on parameters in Verilog frontent. Conte...Maciej Kurc2019-05-161-2/+2
* | | Make the generated *.tab.hh include all the headers needed to define the union.Henner Zeller2019-05-141-1/+9
|/ /
* | Merge pull request #946 from YosysHQ/clifford/specifyClifford Wolf2019-05-061-22/+295
|\ \
| * \ Merge branch 'master' of github.com:YosysHQ/yosys into clifford/specifyClifford Wolf2019-05-061-2/+8
| |\ \
| * | | Improve $specrule interfaceClifford Wolf2019-04-231-8/+18
| * | | Improve $specrule interfaceClifford Wolf2019-04-231-20/+18
| * | | Add $specrule cells for $setup/$hold/$skew specify rulesClifford Wolf2019-04-231-2/+67
| * | | Rename T_{RISE,FALL}_AVG to T_{RISE,FALL}_TYP to better match verilog std nom...Clifford Wolf2019-04-231-2/+2
| * | | Add specify parserClifford Wolf2019-04-231-22/+222
| | |/ | |/|
* | | verilog_parser: Fix Bison warningBen Widawsky2019-05-051-1/+1
| |/ |/|
* | Merge pull request #988 from YosysHQ/clifford/fix987Clifford Wolf2019-05-041-1/+4
|\ \
| * | Add approximate support for SV "var" keyword, fixes #987Clifford Wolf2019-05-041-1/+4
| |/
* / Add support for SVA "final" keywordClifford Wolf2019-05-041-1/+4
|/
* New behavior for front-end handling of whiteboxesClifford Wolf2019-04-201-5/+5
* Add "whitebox" attribute, add "read_verilog -wb"Clifford Wolf2019-04-181-5/+5
* Fix handling of cases that look like sva labels, fixes #862Clifford Wolf2019-03-101-43/+56
* Also add support for labels on sva module items, fixes #699Clifford Wolf2019-03-081-39/+61
* Add support for SVA labels in read_verilogClifford Wolf2019-03-071-23/+79
* Fix typographical and grammatical errors and inconsistencies.whitequark2019-01-021-3/+3
* verilog_parser: Properly handle recursion when processing attributesSylvain Munaut2018-12-141-19/+29
* Add warning for SV "restrict" without "property"Clifford Wolf2018-11-041-2/+11
* Fix minor typo in error messageClifford Wolf2018-10-251-1/+1
* Rename the generic "Syntax error" message from the Verilog/SystemVerilog pars...Udi Finkelstein2018-10-251-14/+14
generated by cgit v1.2.3 (git 2.25.1) at 2025-01-29 05:50:25 +0000