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* Merge branch 'pr_elab_sys_tasks' of https://github.com/udif/yosys into cliffo...Clifford Wolf2019-06-071-1/+10
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| * Initial implementation of elaboration system tasksUdi Finkelstein2019-05-031-1/+10
* | Cleanup tux3-implicit_named_connectionClifford Wolf2019-06-071-1/+1
* | Merge branch 'implicit_named_connection' of https://github.com/tux3/yosys int...Clifford Wolf2019-06-071-1/+10
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| * | SystemVerilog support for implicit named port connectionstux32019-06-061-9/+17
* | | Fixed memory leak.Maciej Kurc2019-06-051-0/+4
* | | Added support for parsing attributes on port connections.Maciej Kurc2019-05-311-10/+10
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* | fix indentation across filesStefan Biereigel2019-05-231-2/+2
* | make lexer/parser aware of wand/wor net typesStefan Biereigel2019-05-231-1/+7
* | Merge pull request #1013 from antmicro/parameter_attributesClifford Wolf2019-05-161-2/+2
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| * | Added support for parsing attributes on parameters in Verilog frontent. Conte...Maciej Kurc2019-05-161-2/+2
* | | Make the generated *.tab.hh include all the headers needed to define the union.Henner Zeller2019-05-141-1/+9
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* | Merge pull request #946 from YosysHQ/clifford/specifyClifford Wolf2019-05-061-22/+295
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| * \ Merge branch 'master' of github.com:YosysHQ/yosys into clifford/specifyClifford Wolf2019-05-061-2/+8
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| * | | Improve $specrule interfaceClifford Wolf2019-04-231-8/+18
| * | | Improve $specrule interfaceClifford Wolf2019-04-231-20/+18
| * | | Add $specrule cells for $setup/$hold/$skew specify rulesClifford Wolf2019-04-231-2/+67
| * | | Rename T_{RISE,FALL}_AVG to T_{RISE,FALL}_TYP to better match verilog std nom...Clifford Wolf2019-04-231-2/+2
| * | | Add specify parserClifford Wolf2019-04-231-22/+222
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* | | verilog_parser: Fix Bison warningBen Widawsky2019-05-051-1/+1
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* | Merge pull request #988 from YosysHQ/clifford/fix987Clifford Wolf2019-05-041-1/+4
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| * | Add approximate support for SV "var" keyword, fixes #987Clifford Wolf2019-05-041-1/+4
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* / Add support for SVA "final" keywordClifford Wolf2019-05-041-1/+4
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* New behavior for front-end handling of whiteboxesClifford Wolf2019-04-201-5/+5
* Add "whitebox" attribute, add "read_verilog -wb"Clifford Wolf2019-04-181-5/+5
* Fix handling of cases that look like sva labels, fixes #862Clifford Wolf2019-03-101-43/+56
* Also add support for labels on sva module items, fixes #699Clifford Wolf2019-03-081-39/+61
* Add support for SVA labels in read_verilogClifford Wolf2019-03-071-23/+79
* Fix typographical and grammatical errors and inconsistencies.whitequark2019-01-021-3/+3
* verilog_parser: Properly handle recursion when processing attributesSylvain Munaut2018-12-141-19/+29
* Add warning for SV "restrict" without "property"Clifford Wolf2018-11-041-2/+11
* Fix minor typo in error messageClifford Wolf2018-10-251-1/+1
* Rename the generic "Syntax error" message from the Verilog/SystemVerilog pars...Udi Finkelstein2018-10-251-14/+14
* Handle FIXME for modport members without type directly in frontRuben Undheim2018-10-131-6/+8
* Support for 'modports' for System Verilog interfacesRuben Undheim2018-10-121-3/+21
* Synthesis support for SystemVerilog interfacesRuben Undheim2018-10-121-0/+60
* Add "read_verilog -noassert -noassume -assert-assumes"Clifford Wolf2018-09-241-5/+18
* Added support for ommited "parameter" in Verilog-2001 style parameter decl in...Clifford Wolf2018-09-231-3/+9
* Fixed all known specify/endspecify issues, without breaking 'make test'.Udi Finkelstein2018-08-201-12/+12
* Yosys can now parse https://github.com/verilog-to-routing/vtr-verilog-to-rout...Udi Finkelstein2018-08-201-10/+22
* A few minor enhancements to specify block parsing.Udi Finkelstein2018-08-151-2/+13
* Merge pull request #513 from udif/pr_reg_wire_errorClifford Wolf2018-08-151-1/+6
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| * Modified errors into warningsUdi Finkelstein2018-06-051-0/+1
| * This PR should be the base for discussion, do not merge it yet!Udi Finkelstein2018-03-111-1/+5
* | Detect illegal port declaration, e.g input/output/inout keyword must be the f...Udi Finkelstein2018-06-061-3/+6
* | Add statement labels for immediate assertionsClifford Wolf2018-04-131-18/+21
* | Allow "property" in immediate assertionsClifford Wolf2018-04-121-17/+20
* | Add read_verilog anyseq/anyconst/allseq/allconst attribute supportClifford Wolf2018-04-061-1/+33
* | First draft of Verilog parser support for specify blocks and parameters.Udi Finkelstein2018-03-271-2/+167
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* Add $allconst and $allseq cell typesClifford Wolf2018-02-231-1/+3
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