iCE40/yosys - [no description]

	Commit message (Expand)	Author	Age	Files	Lines
*	Fixed trailing whitespaces	Clifford Wolf	2015-07-02	1	-2/+2
*	Added non-std verilog assume() statement	Clifford Wolf	2015-02-26	1	-0/+3
*	Added warning for use of 'z' constants in HDL	Clifford Wolf	2014-11-14	1	-1/+1
*	Changed frontend-api from FILE to std::istream	Clifford Wolf	2014-08-23	1	-1/+4
*	Moved some stuff to kernel/yosys.{h,cc}, using Yosys:: namespace	Clifford Wolf	2014-07-31	1	-1/+5
*	Added read_verilog -sv options, added support for bit, logic,	Clifford Wolf	2014-06-12	1	-0/+3
*	Added Verilog support for "`default_nettype none"	Clifford Wolf	2014-02-17	1	-0/+3
*	Enable {* .. *} feature per default (removes dependency to REJECT feature in ...	Clifford Wolf	2013-11-22	1	-3/+0
*	Added support for include directories with the new '-I' argument of the	Johann Glaser	2013-08-20	1	-1/+2
*	added option '-Dname[=definition]' to command 'read_verilog'	Johann Glaser	2013-05-19	1	-1/+1
*	initial import	Clifford Wolf	2013-01-05	1	-0/+62