| Commit message (Expand) | Author | Age | Files | Lines |
|---|
| * | namespace Yosys | Clifford Wolf | 2014-09-27 | 1 | -16/+16 |
| * | Removed compatbility.{h,cc}: Not using open_memstream/fmemopen anymore | Clifford Wolf | 2014-08-23 | 1 | -4/+1 |
| * | Changed frontend-api from FILE to std::istream | Clifford Wolf | 2014-08-23 | 1 | -6/+6 |
| * | Added support for global tasks and functions | Clifford Wolf | 2014-08-21 | 1 | -4/+4 |
| * | Moved some stuff to kernel/yosys.{h,cc}, using Yosys:: namespace | Clifford Wolf | 2014-07-31 | 1 | -0/+3 |
| * | Using log_assert() instead of assert() | Clifford Wolf | 2014-07-28 | 1 | -1/+0 |
| * | Added read_verilog -sv options, added support for bit, logic, | Clifford Wolf | 2014-06-12 | 1 | -0/+10 |
| * | Improved error message for options after front-end filename arguments | Clifford Wolf | 2014-06-04 | 1 | -1/+1 |
| * | Merged OSX fixes from Siesh1oo with some modifications | Clifford Wolf | 2014-03-13 | 1 | -0/+1 |
| * | Added Verilog support for "`default_nettype none" | Clifford Wolf | 2014-02-17 | 1 | -1/+2 |
| * | Added a warning note about error reporting to read_verilog help message | Clifford Wolf | 2014-02-16 | 1 | -0/+5 |
| * | Implemented read_verilog -defer | Clifford Wolf | 2014-02-13 | 1 | -1/+11 |
| * | Added read_verilog -setattr | Clifford Wolf | 2014-02-05 | 1 | -0/+15 |
| * | Added support for blanks after -I and -D in read_verilog | Clifford Wolf | 2014-02-02 | 1 | -7/+20 |
| * | Added read_verilog -icells option | Clifford Wolf | 2014-01-29 | 1 | -1/+9 |
| * | Added verilog_defaults command | Clifford Wolf | 2014-01-17 | 1 | -0/+66 |
| * | Added verilog frontend -ignore_redef option | Clifford Wolf | 2013-11-24 | 1 | -1/+10 |
| * | Renamed "placeholder" to "blackbox" | Clifford Wolf | 2013-11-22 | 1 | -1/+1 |
| * | Enable {* .. *} feature per default (removes dependency to REJECT feature in ... | Clifford Wolf | 2013-11-22 | 1 | -2/+0 |
| * | Added support for include directories with the new '-I' argument of the | Johann Glaser | 2013-08-20 | 1 | -1/+10 |
| * | Improved ast dumping (ast/verilog frontend) | Clifford Wolf | 2013-08-19 | 1 | -12/+11 |
| * | Enabled AST/Verilog front-end optimizations per default | Clifford Wolf | 2013-06-10 | 1 | -1/+10 |
| * | added option '-Dname[=definition]' to command 'read_verilog' | Johann Glaser | 2013-05-19 | 1 | -1/+16 |
| * | Implemented proper handling of stub placeholder modules | Clifford Wolf | 2013-03-28 | 1 | -1/+9 |
| * | Added mem2reg option to verilog frontend | Clifford Wolf | 2013-03-24 | 1 | -1/+11 |
| * | Added help messages to ilang and verilog frontends | Clifford Wolf | 2013-03-01 | 1 | -1/+46 |
| * | Moved stand-alone libs to libs/ directory and added libs/subcircuit | Clifford Wolf | 2013-02-27 | 1 | -1/+1 |
| * | initial import | Clifford Wolf | 2013-01-05 | 1 | -0/+148 |
