Commit message (Collapse) | Author | Age | Files | Lines | |
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* | For hier_tree::Elaborate() also include SV root modules (bind) | Eddie Hung | 2019-05-03 | 1 | -23/+36 |
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* | Fix verific_parameters construction, use attribute to mark top netlists | Eddie Hung | 2019-05-03 | 2 | -8/+12 |
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* | WIP -chparam support for hierarchy when verific | Eddie Hung | 2019-05-03 | 2 | -12/+17 |
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* | verific_import() changes to avoid ElaborateAll() | Eddie Hung | 2019-05-03 | 1 | -15/+38 |
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* | Add "read -verific" and "read -noverific" | Clifford Wolf | 2019-03-27 | 1 | -6/+28 |
| | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
* | Fix "verific -extnets" for more complex situations | Clifford Wolf | 2019-03-26 | 1 | -15/+71 |
| | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
* | Merge pull request #858 from YosysHQ/clifford/svalabels | Clifford Wolf | 2019-03-09 | 1 | -1/+14 |
|\ | | | | | Add support for using SVA labels in yosys-smtbmc console output | ||||
| * | Add hack for handling SVA labels via Verific | Clifford Wolf | 2019-03-07 | 1 | -1/+14 |
| | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
* | | Update help message for -chparam | Eddie Hung | 2019-03-09 | 1 | -1/+2 |
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* | | Add -chparam option to verific command | Eddie Hung | 2019-03-09 | 1 | -2/+18 |
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* | | Fix spelling | Eddie Hung | 2019-03-09 | 1 | -1/+1 |
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* | Improve "read" error msg | Clifford Wolf | 2019-02-28 | 1 | -1/+1 |
| | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
* | Check if Verific was built with DB_PRESERVE_INITIAL_VALUE | Clifford Wolf | 2019-02-24 | 1 | -0/+4 |
| | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
* | Remove -m32 Verific eval lib build instructions | Clifford Wolf | 2019-01-04 | 1 | -29/+0 |
| | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
* | Improve VerificImporter support for writes to asymmetric memories | Clifford Wolf | 2019-01-02 | 1 | -22/+35 |
| | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
* | Fix VerificImporter asymmetric memories error message | Clifford Wolf | 2019-01-02 | 1 | -1/+1 |
| | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
* | Fix typographical and grammatical errors and inconsistencies. | whitequark | 2019-01-02 | 1 | -4/+4 |
| | | | | | | | | | | | | The initial list of hits was generated with the codespell command below, and each hit was evaluated and fixed manually while taking context into consideration. DIRS="kernel/ frontends/ backends/ passes/ techlibs/" DIRS="${DIRS} libs/ezsat/ libs/subcircuit" codespell $DIRS -S *.o -L upto,iff,thru,synopsys,uint More hits were found by looking through comments and strings manually. | ||||
* | Improve src tagging (using names and attrs) of cells and wires in verific ↵ | Clifford Wolf | 2018-12-18 | 2 | -99/+160 |
| | | | | | | front-end Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
* | Verific updates | Clifford Wolf | 2018-12-06 | 1 | -53/+0 |
| | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
* | Set Verific flag vhdl_support_variable_slice=1 | Clifford Wolf | 2018-11-09 | 1 | -0/+1 |
| | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
* | Improve Verific importer blackbox handling | Clifford Wolf | 2018-10-07 | 1 | -2/+14 |
| | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
* | Fix compiler warning in verific.cc | Clifford Wolf | 2018-10-05 | 1 | -0/+2 |
| | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
* | Add "verific -L <int>" option | Clifford Wolf | 2018-09-04 | 3 | -2/+16 |
| | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
* | Add "verific -work" help message | Clifford Wolf | 2018-08-22 | 1 | -0/+7 |
| | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
* | Add Verific -work parameter | Clifford Wolf | 2018-08-22 | 1 | -8/+18 |
| | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
* | Add "verific -set-<severity> <msg_id>.." | Clifford Wolf | 2018-08-16 | 1 | -14/+52 |
| | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
* | Verific workaround for VIPER ticket 13851 | Clifford Wolf | 2018-08-16 | 1 | -0/+3 |
| | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
* | Merge pull request #591 from hzeller/virtual-override | Clifford Wolf | 2018-08-15 | 1 | -5/+5 |
|\ | | | | | Consistent use of 'override' for virtual methods in derived classes. | ||||
| * | Consistent use of 'override' for virtual methods in derived classes. | Henner Zeller | 2018-07-20 | 1 | -5/+5 |
| | | | | | | | | | | | | | | | | | | o Not all derived methods were marked 'override', but it is a great feature of C++11 that we should make use of. o While at it: touched header files got a -*- c++ -*- for emacs to provide support for that language. o use YS_OVERRIDE for all override keywords (though we should probably use the plain keyword going forward now that C++11 is established) | ||||
* | | Verific: Produce errors for instantiating unknown module | Clifford Wolf | 2018-07-22 | 1 | -0/+3 |
|/ | | | | | | | | Because if the unknown module is connected to any constants, Verific will actually break all constants in the same module, even if they have nothing to do structurally with that instance of an unknown module. Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
* | Fix handling of eventually properties in verific importer | Clifford Wolf | 2018-07-17 | 1 | -2/+4 |
| | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
* | Fix verific -vlog-incdir and -vlog-libdir handling | Clifford Wolf | 2018-07-16 | 1 | -2/+13 |
| | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
* | Fix "read -incdir" | Clifford Wolf | 2018-07-16 | 1 | -1/+1 |
| | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
* | Add "read -incdir" | Clifford Wolf | 2018-07-16 | 1 | -0/+19 |
| | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
* | Fix verific eventually handling | Clifford Wolf | 2018-06-29 | 1 | -6/+5 |
| | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
* | Add verific support for eventually properties | Clifford Wolf | 2018-06-29 | 1 | -5/+105 |
| | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
* | Add "verific -formal" and "read -formal" | Clifford Wolf | 2018-06-29 | 1 | -7/+15 |
| | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
* | Add "read -sv -D" support | Clifford Wolf | 2018-06-28 | 1 | -2/+25 |
| | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
* | Add "read -undef" | Clifford Wolf | 2018-06-28 | 1 | -0/+32 |
| | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
* | Add YOSYS_NOVERIFIC env variable for temporarily disabling verific | Clifford Wolf | 2018-06-22 | 1 | -22/+40 |
| | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
* | Add simplified "read" command, enable extnets in implicit Verific import | Clifford Wolf | 2018-06-21 | 1 | -0/+84 |
| | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
* | Add automatic verific import in hierarchy command | Clifford Wolf | 2018-06-20 | 2 | -0/+56 |
| | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
* | Add (* gclk *) attribute support | Clifford Wolf | 2018-06-01 | 2 | -0/+11 |
| | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
* | Add comment to VIPER #13453 work-around | Clifford Wolf | 2018-05-28 | 1 | -0/+1 |
| | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
* | Fix Verific handling of single-bit anyseq/anyconst wires | Clifford Wolf | 2018-05-25 | 1 | -2/+4 |
| | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
* | Fix VerificClocking for cases where Verific generates chains of PRIM_SVA_POSEDGE | Clifford Wolf | 2018-05-24 | 1 | -1/+1 |
| | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
* | Fix verific handling of anyconst/anyseq attributes | Clifford Wolf | 2018-05-24 | 2 | -16/+28 |
| | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
* | Fix handling of anyconst/anyseq attrs in VHDL code via Verific | Clifford Wolf | 2018-05-15 | 1 | -6/+6 |
| | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
* | Further improve handling of zero-length SVA consecutive repetition | Clifford Wolf | 2018-05-05 | 1 | -69/+108 |
| | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
* | Fix handling of zero-length SVA consecutive repetition | Clifford Wolf | 2018-05-05 | 1 | -26/+46 |
| | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> |