iCE40/yosys - [no description]

	Commit message (Expand)	Author	Age	Files	Lines
*	Only support Symbiotic EDA flavored Verific	Clifford Wolf	2019-06-02	1	-0/+8
*	Enable Verific flag veri_elaborate_top_level_modules_having_interface_ports, ...	Clifford Wolf	2019-05-30	1	-0/+3
*	For hier_tree::Elaborate() also include SV root modules (bind)	Eddie Hung	2019-05-03	1	-23/+36
*	Fix verific_parameters construction, use attribute to mark top netlists	Eddie Hung	2019-05-03	2	-8/+12
*	WIP -chparam support for hierarchy when verific	Eddie Hung	2019-05-03	2	-12/+17
*	verific_import() changes to avoid ElaborateAll()	Eddie Hung	2019-05-03	1	-15/+38
*	Add "read -verific" and "read -noverific"	Clifford Wolf	2019-03-27	1	-6/+28
*	Fix "verific -extnets" for more complex situations	Clifford Wolf	2019-03-26	1	-15/+71
*	Merge pull request #858 from YosysHQ/clifford/svalabels	Clifford Wolf	2019-03-09	1	-1/+14
\|\
\| *	Add hack for handling SVA labels via Verific	Clifford Wolf	2019-03-07	1	-1/+14
* \|	Update help message for -chparam	Eddie Hung	2019-03-09	1	-1/+2
* \|	Add -chparam option to verific command	Eddie Hung	2019-03-09	1	-2/+18
* \|	Fix spelling	Eddie Hung	2019-03-09	1	-1/+1
\|/
*	Improve "read" error msg	Clifford Wolf	2019-02-28	1	-1/+1
*	Check if Verific was built with DB_PRESERVE_INITIAL_VALUE	Clifford Wolf	2019-02-24	1	-0/+4
*	Remove -m32 Verific eval lib build instructions	Clifford Wolf	2019-01-04	1	-29/+0
*	Improve VerificImporter support for writes to asymmetric memories	Clifford Wolf	2019-01-02	1	-22/+35
*	Fix VerificImporter asymmetric memories error message	Clifford Wolf	2019-01-02	1	-1/+1
*	Fix typographical and grammatical errors and inconsistencies.	whitequark	2019-01-02	1	-4/+4
*	Improve src tagging (using names and attrs) of cells and wires in verific fro...	Clifford Wolf	2018-12-18	2	-99/+160
*	Verific updates	Clifford Wolf	2018-12-06	1	-53/+0
*	Set Verific flag vhdl_support_variable_slice=1	Clifford Wolf	2018-11-09	1	-0/+1
*	Improve Verific importer blackbox handling	Clifford Wolf	2018-10-07	1	-2/+14
*	Fix compiler warning in verific.cc	Clifford Wolf	2018-10-05	1	-0/+2
*	Add "verific -L <int>" option	Clifford Wolf	2018-09-04	3	-2/+16
*	Add "verific -work" help message	Clifford Wolf	2018-08-22	1	-0/+7
*	Add Verific -work parameter	Clifford Wolf	2018-08-22	1	-8/+18
*	Add "verific -set-<severity> <msg_id>.."	Clifford Wolf	2018-08-16	1	-14/+52
*	Verific workaround for VIPER ticket 13851	Clifford Wolf	2018-08-16	1	-0/+3
*	Merge pull request #591 from hzeller/virtual-override	Clifford Wolf	2018-08-15	1	-5/+5
\|\
\| *	Consistent use of 'override' for virtual methods in derived classes.	Henner Zeller	2018-07-20	1	-5/+5
* \|	Verific: Produce errors for instantiating unknown module	Clifford Wolf	2018-07-22	1	-0/+3
\|/
*	Fix handling of eventually properties in verific importer	Clifford Wolf	2018-07-17	1	-2/+4
*	Fix verific -vlog-incdir and -vlog-libdir handling	Clifford Wolf	2018-07-16	1	-2/+13
*	Fix "read -incdir"	Clifford Wolf	2018-07-16	1	-1/+1
*	Add "read -incdir"	Clifford Wolf	2018-07-16	1	-0/+19
*	Fix verific eventually handling	Clifford Wolf	2018-06-29	1	-6/+5
*	Add verific support for eventually properties	Clifford Wolf	2018-06-29	1	-5/+105
*	Add "verific -formal" and "read -formal"	Clifford Wolf	2018-06-29	1	-7/+15
*	Add "read -sv -D" support	Clifford Wolf	2018-06-28	1	-2/+25
*	Add "read -undef"	Clifford Wolf	2018-06-28	1	-0/+32
*	Add YOSYS_NOVERIFIC env variable for temporarily disabling verific	Clifford Wolf	2018-06-22	1	-22/+40
*	Add simplified "read" command, enable extnets in implicit Verific import	Clifford Wolf	2018-06-21	1	-0/+84
*	Add automatic verific import in hierarchy command	Clifford Wolf	2018-06-20	2	-0/+56
*	Add (* gclk *) attribute support	Clifford Wolf	2018-06-01	2	-0/+11
*	Add comment to VIPER #13453 work-around	Clifford Wolf	2018-05-28	1	-0/+1
*	Fix Verific handling of single-bit anyseq/anyconst wires	Clifford Wolf	2018-05-25	1	-2/+4
*	Fix VerificClocking for cases where Verific generates chains of PRIM_SVA_POSEDGE	Clifford Wolf	2018-05-24	1	-1/+1
*	Fix verific handling of anyconst/anyseq attributes	Clifford Wolf	2018-05-24	2	-16/+28
*	Fix handling of anyconst/anyseq attrs in VHDL code via Verific	Clifford Wolf	2018-05-15	1	-6/+6