iCE40/yosys - [no description]

	Commit message (Expand)	Author	Age	Files	Lines
*	Enable bison to be customized	Fabio Utzig	2015-01-08	1	-1/+1
*	Fixed memory->start_offset handling	Clifford Wolf	2015-01-01	1	-0/+3
*	Added Yosys::{dict,nodict,vector} container types	Clifford Wolf	2014-12-26	1	-1/+1
*	Re-introduced Yosys::readsome() helper function	Clifford Wolf	2014-10-23	1	-5/+1
*	Updated .gitignore file for ilang and verilog frontends	Clifford Wolf	2014-10-15	1	-4/+4
*	Updated lexers & parsers to include prefixes	William Speirs	2014-10-15	3	-13/+17
*	Fixed win32 troubles with f.readsome()	Clifford Wolf	2014-10-11	1	-1/+1
*	namespace Yosys	Clifford Wolf	2014-09-27	2	-3/+5
*	Changed frontend-api from FILE to std::istream	Clifford Wolf	2014-08-23	4	-6/+10
*	Added module->ports	Clifford Wolf	2014-08-14	1	-0/+1
*	Renamed port access function on RTLIL::Cell, added param access functions	Clifford Wolf	2014-07-31	1	-2/+2
*	Added module->design and cell->module, wire->module pointers	Clifford Wolf	2014-07-31	1	-2/+2
*	Moved some stuff to kernel/yosys.{h,cc}, using Yosys:: namespace	Clifford Wolf	2014-07-31	3	-4/+15
*	Added wire->upto flag for signals such as "wire [0:7] x;"	Clifford Wolf	2014-07-28	2	-1/+5
*	Fixed ilang parser for new RTLIL API	Clifford Wolf	2014-07-27	1	-10/+10
*	Changed a lot of code to the new RTLIL::Wire constructors	Clifford Wolf	2014-07-26	1	-3/+2
*	Added RTLIL::Cell::has(portname)	Clifford Wolf	2014-07-26	1	-1/+1
*	Manual fixes for new cell connections API	Clifford Wolf	2014-07-26	1	-1/+1
*	Changed users of cell->connections_ to the new API (sed command)	Clifford Wolf	2014-07-26	1	-2/+2
*	Renamed RTLIL::{Module,Cell}::connections to connections_	Clifford Wolf	2014-07-26	1	-3/+3
*	Use only module->addCell() and module->remove() to create and delete cells	Clifford Wolf	2014-07-25	1	-4/+1
*	Added "make PRETTY=1"	Clifford Wolf	2014-07-24	1	-3/+3
*	Refactoring {SigSpec\|SigChunk}(RTLIL::Wire *wire, ..) constructor -- step 3/3	Clifford Wolf	2014-07-23	1	-2/+2
*	Refactoring {SigSpec\|SigChunk}(RTLIL::Wire *wire, ..) constructor -- step 2/3	Clifford Wolf	2014-07-23	1	-2/+2
*	SigSpec refactoring: change RTLIL::SigSpec::size() to be read-only	Clifford Wolf	2014-07-22	1	-37/+6
*	SigSpec refactoring: using the accessor functions everywhere	Clifford Wolf	2014-07-22	1	-14/+14
*	SigSpec refactoring: renamed chunks and width to __chunks and __width	Clifford Wolf	2014-07-22	1	-14/+14
*	Fixed ilang parsing of process attributes	Clifford Wolf	2014-07-22	1	-0/+1
*	Fixed make rules for ilang parser	Clifford Wolf	2014-07-22	1	-1/+3
*	Added "autoidx" statement to ilang file format	Clifford Wolf	2014-07-21	2	-25/+10
*	Fixed clang -Wdeprecated-register warnings	Clifford Wolf	2014-04-20	1	-0/+7
*	Replaced depricated %name-prefix= bison directive	Clifford Wolf	2014-04-20	1	-1/+1
*	Bugfix in ilang frontend autoidx recovery	Clifford Wolf	2014-03-07	1	-2/+2
*	renamed ilang "scope error" to "ilang error"	Clifford Wolf	2014-02-11	1	-9/+9
*	Improved ilang parser error messages	Clifford Wolf	2014-02-09	1	-9/+9
*	Fixed comment/eol parsing in ilang frontend	Clifford Wolf	2014-02-01	2	-22/+25
*	Added updating of RTLIL::autoidx to ilang frontend	Clifford Wolf	2014-01-03	1	-1/+23
*	Replaced signed_parameters API with CONST_FLAG_SIGNED	Clifford Wolf	2013-12-04	1	-1/+1
*	Added support for signed parameters in ilang	Clifford Wolf	2013-11-24	2	-1/+8
*	Remove auto_wire framework (smarter than the verilog standard)	Clifford Wolf	2013-11-24	2	-5/+1
*	Major improvements in mem2reg and added "init" sync rules	Clifford Wolf	2013-11-21	2	-1/+8
*	Fixed ilang parser: memory width	Clifford Wolf	2013-11-20	1	-1/+1
*	Fixed parsing of value-less attributes in ilang	Clifford Wolf	2013-10-23	1	-1/+1
*	Fixed memory leak in ilang frontend	Clifford Wolf	2013-05-23	1	-0/+1
*	Added help messages to ilang and verilog frontends	Clifford Wolf	2013-03-01	1	-1/+11
*	added .gitignore files	Clifford Wolf	2013-01-05	1	-0/+4
*	initial import	Clifford Wolf	2013-01-05	5	-0/+648