| Commit message (Expand) | Author | Age | Files | Lines |
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| * | read_ilang: do bounds checking on bit indices | Marcin Kościelnicki | 2019-11-27 | 1 | -0/+4 |
| * | Allow attributes on individual switch cases in RTLIL. | whitequark | 2019-07-08 | 1 | -4/+9 |
| * | Make the generated *.tab.hh include all the headers needed to define the union. | Henner Zeller | 2019-05-14 | 1 | -1/+9 |
| * | Merge pull request #946 from YosysHQ/clifford/specify | Clifford Wolf | 2019-05-06 | 2 | -1/+8 |
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| | * | Add "real" keyword to ilang format | Clifford Wolf | 2019-05-06 | 2 | -1/+8 |
| * | | Fix the other bison warning in ilang_parser.y | Clifford Wolf | 2019-05-06 | 1 | -1/+1 |
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| * | Add "read_ilang -lib" | Clifford Wolf | 2019-04-05 | 3 | -3/+14 |
| * | Add "read_ilang -[no]overwrite" | Clifford Wolf | 2018-12-23 | 3 | -4/+54 |
| * | read_ilang: allow slicing sigspecs. | whitequark | 2018-12-16 | 1 | -10/+6 |
| * | Add "make coverage" | Clifford Wolf | 2018-08-27 | 3 | -6/+5 |
| * | Consistent use of 'override' for virtual methods in derived classes. | Henner Zeller | 2018-07-20 | 1 | -2/+2 |
| * | Added avail params to ilang format, check module params in 'hierarchy -check' | Clifford Wolf | 2016-10-22 | 1 | -1/+7 |
| * | Added $global_clock verilog syntax support for creating $ff cells | Clifford Wolf | 2016-10-14 | 2 | -1/+8 |
| * | Added "yosys -D" feature | Clifford Wolf | 2016-04-21 | 1 | -1/+1 |
| * | Fixed oom bug in ilang parser | Clifford Wolf | 2015-11-29 | 1 | -2/+2 |
| * | Fixed performance bug in ilang parser | Clifford Wolf | 2015-11-27 | 1 | -6/+12 |
| * | Import more std:: stuff into Yosys namespace | Clifford Wolf | 2015-10-25 | 1 | -1/+1 |
| * | Adjust makefiles to work with out-of-tree builds | Clifford Wolf | 2015-08-12 | 3 | -4/+6 |
| * | Fixed trailing whitespaces | Clifford Wolf | 2015-07-02 | 4 | -8/+8 |
| * | Enable bison to be customized | Fabio Utzig | 2015-01-08 | 1 | -1/+1 |
| * | Fixed memory->start_offset handling | Clifford Wolf | 2015-01-01 | 1 | -0/+3 |
| * | Added Yosys::{dict,nodict,vector} container types | Clifford Wolf | 2014-12-26 | 1 | -1/+1 |
| * | Re-introduced Yosys::readsome() helper function | Clifford Wolf | 2014-10-23 | 1 | -5/+1 |
| * | Updated .gitignore file for ilang and verilog frontends | Clifford Wolf | 2014-10-15 | 1 | -4/+4 |
| * | Updated lexers & parsers to include prefixes | William Speirs | 2014-10-15 | 3 | -13/+17 |
| * | Fixed win32 troubles with f.readsome() | Clifford Wolf | 2014-10-11 | 1 | -1/+1 |
| * | namespace Yosys | Clifford Wolf | 2014-09-27 | 2 | -3/+5 |
| * | Changed frontend-api from FILE to std::istream | Clifford Wolf | 2014-08-23 | 4 | -6/+10 |
| * | Added module->ports | Clifford Wolf | 2014-08-14 | 1 | -0/+1 |
| * | Renamed port access function on RTLIL::Cell, added param access functions | Clifford Wolf | 2014-07-31 | 1 | -2/+2 |
| * | Added module->design and cell->module, wire->module pointers | Clifford Wolf | 2014-07-31 | 1 | -2/+2 |
| * | Moved some stuff to kernel/yosys.{h,cc}, using Yosys:: namespace | Clifford Wolf | 2014-07-31 | 3 | -4/+15 |
| * | Added wire->upto flag for signals such as "wire [0:7] x;" | Clifford Wolf | 2014-07-28 | 2 | -1/+5 |
| * | Fixed ilang parser for new RTLIL API | Clifford Wolf | 2014-07-27 | 1 | -10/+10 |
| * | Changed a lot of code to the new RTLIL::Wire constructors | Clifford Wolf | 2014-07-26 | 1 | -3/+2 |
| * | Added RTLIL::Cell::has(portname) | Clifford Wolf | 2014-07-26 | 1 | -1/+1 |
| * | Manual fixes for new cell connections API | Clifford Wolf | 2014-07-26 | 1 | -1/+1 |
| * | Changed users of cell->connections_ to the new API (sed command) | Clifford Wolf | 2014-07-26 | 1 | -2/+2 |
| * | Renamed RTLIL::{Module,Cell}::connections to connections_ | Clifford Wolf | 2014-07-26 | 1 | -3/+3 |
| * | Use only module->addCell() and module->remove() to create and delete cells | Clifford Wolf | 2014-07-25 | 1 | -4/+1 |
| * | Added "make PRETTY=1" | Clifford Wolf | 2014-07-24 | 1 | -3/+3 |
| * | Refactoring {SigSpec|SigChunk}(RTLIL::Wire *wire, ..) constructor -- step 3/3 | Clifford Wolf | 2014-07-23 | 1 | -2/+2 |
| * | Refactoring {SigSpec|SigChunk}(RTLIL::Wire *wire, ..) constructor -- step 2/3 | Clifford Wolf | 2014-07-23 | 1 | -2/+2 |
| * | SigSpec refactoring: change RTLIL::SigSpec::size() to be read-only | Clifford Wolf | 2014-07-22 | 1 | -37/+6 |
| * | SigSpec refactoring: using the accessor functions everywhere | Clifford Wolf | 2014-07-22 | 1 | -14/+14 |
| * | SigSpec refactoring: renamed chunks and width to __chunks and __width | Clifford Wolf | 2014-07-22 | 1 | -14/+14 |
| * | Fixed ilang parsing of process attributes | Clifford Wolf | 2014-07-22 | 1 | -0/+1 |
| * | Fixed make rules for ilang parser | Clifford Wolf | 2014-07-22 | 1 | -1/+3 |
| * | Added "autoidx" statement to ilang file format | Clifford Wolf | 2014-07-21 | 2 | -25/+10 |
| * | Fixed clang -Wdeprecated-register warnings | Clifford Wolf | 2014-04-20 | 1 | -0/+7 |
