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* Enable bison to be customizedFabio Utzig2015-01-081-1/+1
* Fixed memory->start_offset handlingClifford Wolf2015-01-011-0/+3
* Added Yosys::{dict,nodict,vector} container typesClifford Wolf2014-12-261-1/+1
* Re-introduced Yosys::readsome() helper functionClifford Wolf2014-10-231-5/+1
* Updated .gitignore file for ilang and verilog frontendsClifford Wolf2014-10-151-4/+4
* Updated lexers & parsers to include prefixesWilliam Speirs2014-10-153-13/+17
* Fixed win32 troubles with f.readsome()Clifford Wolf2014-10-111-1/+1
* namespace YosysClifford Wolf2014-09-272-3/+5
* Changed frontend-api from FILE to std::istreamClifford Wolf2014-08-234-6/+10
* Added module->portsClifford Wolf2014-08-141-0/+1
* Renamed port access function on RTLIL::Cell, added param access functionsClifford Wolf2014-07-311-2/+2
* Added module->design and cell->module, wire->module pointersClifford Wolf2014-07-311-2/+2
* Moved some stuff to kernel/yosys.{h,cc}, using Yosys:: namespaceClifford Wolf2014-07-313-4/+15
* Added wire->upto flag for signals such as "wire [0:7] x;"Clifford Wolf2014-07-282-1/+5
* Fixed ilang parser for new RTLIL APIClifford Wolf2014-07-271-10/+10
* Changed a lot of code to the new RTLIL::Wire constructorsClifford Wolf2014-07-261-3/+2
* Added RTLIL::Cell::has(portname)Clifford Wolf2014-07-261-1/+1
* Manual fixes for new cell connections APIClifford Wolf2014-07-261-1/+1
* Changed users of cell->connections_ to the new API (sed command)Clifford Wolf2014-07-261-2/+2
* Renamed RTLIL::{Module,Cell}::connections to connections_Clifford Wolf2014-07-261-3/+3
* Use only module->addCell() and module->remove() to create and delete cellsClifford Wolf2014-07-251-4/+1
* Added "make PRETTY=1"Clifford Wolf2014-07-241-3/+3
* Refactoring {SigSpec|SigChunk}(RTLIL::Wire *wire, ..) constructor -- step 3/3Clifford Wolf2014-07-231-2/+2
* Refactoring {SigSpec|SigChunk}(RTLIL::Wire *wire, ..) constructor -- step 2/3Clifford Wolf2014-07-231-2/+2
* SigSpec refactoring: change RTLIL::SigSpec::size() to be read-onlyClifford Wolf2014-07-221-37/+6
* SigSpec refactoring: using the accessor functions everywhereClifford Wolf2014-07-221-14/+14
* SigSpec refactoring: renamed chunks and width to __chunks and __widthClifford Wolf2014-07-221-14/+14
* Fixed ilang parsing of process attributesClifford Wolf2014-07-221-0/+1
* Fixed make rules for ilang parserClifford Wolf2014-07-221-1/+3
* Added "autoidx" statement to ilang file formatClifford Wolf2014-07-212-25/+10
* Fixed clang -Wdeprecated-register warningsClifford Wolf2014-04-201-0/+7
* Replaced depricated %name-prefix= bison directiveClifford Wolf2014-04-201-1/+1
* Bugfix in ilang frontend autoidx recoveryClifford Wolf2014-03-071-2/+2
* renamed ilang "scope error" to "ilang error"Clifford Wolf2014-02-111-9/+9
* Improved ilang parser error messagesClifford Wolf2014-02-091-9/+9
* Fixed comment/eol parsing in ilang frontendClifford Wolf2014-02-012-22/+25
* Added updating of RTLIL::autoidx to ilang frontendClifford Wolf2014-01-031-1/+23
* Replaced signed_parameters API with CONST_FLAG_SIGNEDClifford Wolf2013-12-041-1/+1
* Added support for signed parameters in ilangClifford Wolf2013-11-242-1/+8
* Remove auto_wire framework (smarter than the verilog standard)Clifford Wolf2013-11-242-5/+1
* Major improvements in mem2reg and added "init" sync rulesClifford Wolf2013-11-212-1/+8
* Fixed ilang parser: memory widthClifford Wolf2013-11-201-1/+1
* Fixed parsing of value-less attributes in ilangClifford Wolf2013-10-231-1/+1
* Fixed memory leak in ilang frontendClifford Wolf2013-05-231-0/+1
* Added help messages to ilang and verilog frontendsClifford Wolf2013-03-011-1/+11
* added .gitignore filesClifford Wolf2013-01-051-0/+4
* initial importClifford Wolf2013-01-055-0/+648