iCE40/yosys - [no description]

	Commit message (Expand)	Author	Age	Files	Lines
*	Manual fixes for new cell connections API	Clifford Wolf	2014-07-26	1	-1/+1
*	Changed users of cell->connections_ to the new API (sed command)	Clifford Wolf	2014-07-26	1	-2/+2
*	Renamed RTLIL::{Module,Cell}::connections to connections_	Clifford Wolf	2014-07-26	1	-3/+3
*	Use only module->addCell() and module->remove() to create and delete cells	Clifford Wolf	2014-07-25	1	-4/+1
*	Refactoring {SigSpec\|SigChunk}(RTLIL::Wire *wire, ..) constructor -- step 3/3	Clifford Wolf	2014-07-23	1	-2/+2
*	Refactoring {SigSpec\|SigChunk}(RTLIL::Wire *wire, ..) constructor -- step 2/3	Clifford Wolf	2014-07-23	1	-2/+2
*	SigSpec refactoring: change RTLIL::SigSpec::size() to be read-only	Clifford Wolf	2014-07-22	1	-37/+6
*	SigSpec refactoring: using the accessor functions everywhere	Clifford Wolf	2014-07-22	1	-14/+14
*	SigSpec refactoring: renamed chunks and width to __chunks and __width	Clifford Wolf	2014-07-22	1	-14/+14
*	Fixed ilang parsing of process attributes	Clifford Wolf	2014-07-22	1	-0/+1
*	Added "autoidx" statement to ilang file format	Clifford Wolf	2014-07-21	1	-1/+7
*	Replaced depricated %name-prefix= bison directive	Clifford Wolf	2014-04-20	1	-1/+1
*	renamed ilang "scope error" to "ilang error"	Clifford Wolf	2014-02-11	1	-9/+9
*	Improved ilang parser error messages	Clifford Wolf	2014-02-09	1	-9/+9
*	Fixed comment/eol parsing in ilang frontend	Clifford Wolf	2014-02-01	1	-21/+24
*	Replaced signed_parameters API with CONST_FLAG_SIGNED	Clifford Wolf	2013-12-04	1	-1/+1
*	Added support for signed parameters in ilang	Clifford Wolf	2013-11-24	1	-1/+7
*	Remove auto_wire framework (smarter than the verilog standard)	Clifford Wolf	2013-11-24	1	-4/+1
*	Major improvements in mem2reg and added "init" sync rules	Clifford Wolf	2013-11-21	1	-1/+7
*	Fixed ilang parser: memory width	Clifford Wolf	2013-11-20	1	-1/+1
*	Fixed memory leak in ilang frontend	Clifford Wolf	2013-05-23	1	-0/+1
*	initial import	Clifford Wolf	2013-01-05	1	-0/+416