iCE40/yosys - clone of https://github.com/YosysHQ/yosys

	Commit message (Expand)	Author	Age	Files	Lines
*	Added wire->upto flag for signals such as "wire [0:7] x;"	Clifford Wolf	2014-07-28	1	-0/+1
*	Added "autoidx" statement to ilang file format	Clifford Wolf	2014-07-21	1	-24/+3
*	Fixed clang -Wdeprecated-register warnings	Clifford Wolf	2014-04-20	1	-0/+7
*	Bugfix in ilang frontend autoidx recovery	Clifford Wolf	2014-03-07	1	-2/+2
*	Fixed comment/eol parsing in ilang frontend	Clifford Wolf	2014-02-01	1	-1/+1
*	Added updating of RTLIL::autoidx to ilang frontend	Clifford Wolf	2014-01-03	1	-1/+23
*	Added support for signed parameters in ilang	Clifford Wolf	2013-11-24	1	-0/+1
*	Remove auto_wire framework (smarter than the verilog standard)	Clifford Wolf	2013-11-24	1	-1/+0
*	Major improvements in mem2reg and added "init" sync rules	Clifford Wolf	2013-11-21	1	-0/+1
*	Fixed parsing of value-less attributes in ilang	Clifford Wolf	2013-10-23	1	-1/+1
*	initial import	Clifford Wolf	2013-01-05	1	-0/+122