| Commit message (Expand) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | Added updating of RTLIL::autoidx to ilang frontend | Clifford Wolf | 2014-01-03 | 1 | -1/+23 |
| * | Added support for signed parameters in ilang | Clifford Wolf | 2013-11-24 | 1 | -0/+1 |
| * | Remove auto_wire framework (smarter than the verilog standard) | Clifford Wolf | 2013-11-24 | 1 | -1/+0 |
| * | Major improvements in mem2reg and added "init" sync rules | Clifford Wolf | 2013-11-21 | 1 | -0/+1 |
| * | Fixed parsing of value-less attributes in ilang | Clifford Wolf | 2013-10-23 | 1 | -1/+1 |
| * | initial import | Clifford Wolf | 2013-01-05 | 1 | -0/+122 |
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index : iCE40/yosys | |
| clone of https://github.com/YosysHQ/yosys |
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