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* Index struct/union members within corresponding wire chunksDag Lem2023-03-054-32/+67
* Out of bounds checking for struct/union membersDag Lem2023-02-191-5/+18
* Support for data and array queries on struct/union item expressionsDag Lem2023-02-151-12/+49
* Merge pull request #3661 from daglem/struct-array-range-offsetJannis Harder2023-02-151-22/+31
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| * Handle range offsets in packed arrays within packed structsDag Lem2023-02-051-22/+31
* | Resolve package types in interfaces (#3658)Dag Lem2023-02-121-3/+3
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* Handle struct members of union type (#3641)Dag Lem2023-01-292-2/+2
* Fixes for some of clang scan-build detected issuesMiodrag Milanovic2023-01-172-3/+3
* Merge pull request #3467 from jix/fix_cellarray_simplifyJannis Harder2022-12-191-0/+2
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| * simplify: Do not recursively simplify AST_CELL within AST_CELLARRAYJannis Harder2022-12-071-0/+2
* | Made make_struct_member_range side-effect-free againDag Lem2022-12-041-20/+20
* | Support for packed multidimensional arrays within packed structsDag Lem2022-12-031-98/+78
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* Merge pull request #3551 from daglem/struct-array-swapped-rangeJannis Harder2022-12-012-21/+61
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| * Added asserts for current limitation of array dimensions in packed structsDag Lem2022-11-301-0/+8
| * Check for all cases of currently unsupported array dimensions in packed structsDag Lem2022-11-301-10/+13
| * Support for swapped ranges in second array dimensionDag Lem2022-11-231-3/+10
| * Support for arrays with swapped ranges within structsDag Lem2022-11-122-10/+32
* | verilog: Support module-scoped task/function callsZachary Snow2022-10-291-0/+4
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* Encode filename unprintable charsMiodrag Milanovic2022-08-082-26/+26
* verilog: fix width/sign detection for functionsZachary Snow2022-05-301-5/+7
* verilog: fix size and signedness of array querying functionsJannis Harder2022-05-302-3/+2
* verilog: fix $past's signednessJannis Harder2022-05-252-1/+2
* verilog: fix signedness when removing unreachable casesJannis Harder2022-05-241-0/+1
* sv: fix always_comb auto nosync for nested and function blocksZachary Snow2022-04-051-1/+11
* Fix access to whole sub-structs (#3086)Kamil Rakoczy2022-02-142-6/+18
* verilog: fix dynamic dynamic range asgn elabZachary Snow2022-02-111-17/+34
* verilog: fix const func eval with upto variablesZachary Snow2022-02-112-3/+11
* fix dumpAst() compilation warningZachary Snow2022-01-181-1/+1
* sv: auto add nosync to certain always_comb local varsZachary Snow2022-01-071-0/+127
* sv: fix size cast internal expression extensionZachary Snow2022-01-071-2/+9
* sv: fix size cast clipping expression widthZachary Snow2022-01-031-1/+2
* fix width detection of array querying function in case and case item expressionsZachary Snow2021-12-172-2/+5
* Support parameters using struct as a wiretype (#3050)Kamil Rakoczy2021-11-161-7/+23
* genrtlil: Fix displaying debug info in packagesKamil Rakoczy2021-11-101-1/+2
* verilog: use derived module info to elaborate cell connectionsZachary Snow2021-10-254-41/+291
* Split out logic for reprocessing an AstModuleRupert Swarbrick2021-10-252-24/+57
* verilog: fix multiple AST_PREFIX scope resolution issuesZachary Snow2021-09-211-4/+9
* Generate an RTLIL representation of bind constructsRupert Swarbrick2021-08-136-2/+193
* genrtlil: add width detection for AST_PREFIX nodesZachary Snow2021-07-291-0/+8
* verilog: Emit $meminit_v2 cell.Marcelina Kościelnicka2021-07-284-51/+83
* Add support for parsing the SystemVerilog 'bind' constructRupert Swarbrick2021-07-163-1/+8
* sv: fix two struct access bugsZachary Snow2021-07-153-1/+10
* rtlil: Make Process handling more uniform with Cell and Wire.Marcelina Kościelnicka2021-07-121-3/+1
* sv: fix a few struct and enum memory leaksZachary Snow2021-07-061-0/+7
* ast: delete wires and localparams after finishing const evaluationXiretza2021-06-141-0/+8
* verilog: fix leaking ASTNodesXiretza2021-06-141-0/+5
* ast: fix error condition causing assert to failXiretza2021-06-141-2/+1
* Merge pull request #2817 from YosysHQ/claire/fixemailsClaire Xen2021-06-095-5/+5
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| * Fixing old e-mail addresses and deadnamesClaire Xenia Wolf2021-06-085-5/+5
* | verilog: check for module scope identifiers during width detectionZachary Snow2021-06-083-13/+30
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