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* Add force_downto and force_upto wire attributes.Marcelina Kościelnicka2020-05-192-1/+20
* Merge pull request #2027 from YosysHQ/eddie/verilog_neg_uptoClaire Wolf2020-05-141-1/+1
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| * ast: swap range regardless of range_left >= 0Eddie Hung2020-05-041-1/+1
* | Merge pull request #2022 from Xiretza/fallthroughswhitequark2020-05-082-4/+5
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| * | Add YS_FALLTHROUGH macro to mark case fall-throughXiretza2020-05-072-4/+5
* | | Merge pull request #2005 from YosysHQ/claire/fix1990Claire Wolf2020-05-074-14/+80
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| * | Fix handling of signed indices in bit slicesClaire Wolf2020-05-021-3/+8
| * | Add AST_SELFSZ and improve handling of bit slicesClaire Wolf2020-05-024-5/+20
| * | Add "nowrshmsk" attribute, fix shift-and-mask bit slice write for signed offs...Claire Wolf2020-05-024-7/+53
* | | Merge pull request #2025 from YosysHQ/eddie/frontend_cleanupEddie Hung2020-05-052-13/+13
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| * | | frontend: cleanup to use more ID::*, more dict<> instead of map<>Eddie Hung2020-05-042-13/+13
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* / | verilog: set src attribute for primitivesEddie Hung2020-05-041-1/+3
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* | Merge pull request #1996 from boqwxp/rtlil_source_locationsEddie Hung2020-05-041-13/+13
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| * frontend: Include complete source location instead of just `location.first_li...Alberto Gonzalez2020-05-011-13/+13
* | Clear current_scope when done with RTLIL generation, fixes #1837Claire Wolf2020-04-221-0/+4
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* ilang, ast: Store parameter order and default value information.Marcelina Kościelnicka2020-04-212-3/+4
* Merge pull request #1851 from YosysHQ/claire/bitselwriteClaire Wolf2020-04-214-15/+207
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| * Make mask-and-shift the default for bitselwriteClaire Wolf2020-04-161-1/+1
| * Add LookaheadRewriter for proper bitselwrite supportClaire Wolf2020-04-164-4/+144
| * Improved rewrite code for writing to bit slice (disabled for now)Claire Wolf2020-04-151-12/+64
* | Merge pull request #1961 from whitequark/paramod-original-namewhitequark2020-04-211-0/+3
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| * | ast, rpc: record original name of $paramod\* as \hdlname attribute.whitequark2020-04-181-0/+3
* | | Extend support for format strings in Verilog front-endClaire Wolf2020-04-181-8/+38
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* / ast: Fix handling of identifiers in the global scopeDavid Shah2020-04-162-2/+7
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* Merge pull request #1918 from whitequark/simplify-improve_enumwhitequark2020-04-151-5/+3
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| * ast/simplify: improve enum handling.whitequark2020-04-151-5/+3
* | Fix 5bba9c3, closes #1876Claire Wolf2020-04-141-7/+13
* | Merge pull request #1879 from jjj11x/jjj11x/package_declwhitequark2020-04-141-0/+23
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| * | support using previously declared types/localparams/params in packageJeff Wang2020-04-071-0/+23
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* / duplicated enum item names should result in an errorJeff Wang2020-04-071-2/+3
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* Merge pull request #1853 from YosysHQ/eddie/fix_dynsliceEddie Hung2020-04-021-1/+2
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| * ast: cap dynamic range select to size of signal, suppresses warningsEddie Hung2020-04-011-1/+2
* | kernel: big fat patch to use more ID::*, otherwise ID(*)Eddie Hung2020-04-023-182/+170
* | kernel: use more ID::*Eddie Hung2020-04-023-53/+53
* | Merge pull request #1845 from YosysHQ/eddie/kernel_speedupEddie Hung2020-04-022-37/+43
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| * | kernel: more pass by const ref, more speedupsEddie Hung2020-03-182-37/+43
* | | Merge pull request #1848 from YosysHQ/eddie/fix_dynsliceClaire Wolf2020-04-011-1/+1
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| * | ast: simplify to fully populate dynamic slicing case transformationEddie Hung2020-03-311-1/+1
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* | Merge pull request #1783 from boqwxp/astcc_cleanupEddie Hung2020-03-301-13/+20
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| * | Add explanatory comment about inefficient wire removal and remove superfluous...Alberto Gonzalez2020-03-301-4/+8
| * | Revert over-aggressive change to a more modest cleanup.Alberto Gonzalez2020-03-271-2/+3
| * | Clean up pseudo-private member usage in `frontends/ast/ast.cc`.Alberto Gonzalez2020-03-191-11/+13
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* | Merge pull request #1607 from whitequark/simplify-simplify-meminitClaire Wolf2020-03-271-63/+82
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| * | ast: avoid intermediate wires/assigns when lowering to AST_MEMINIT.whitequark2020-02-071-65/+84
* | | Simplify was not being called for packages. Broke typedef enums.Peter Crozier2020-03-221-5/+8
* | | Fix NDEBUG warningsEddie Hung2020-03-191-1/+1
* | | Add precise locations for assertshuaixv2020-03-191-0/+1
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* | Merge pull request #1718 from boqwxp/precise_locationsClaire Wolf2020-03-034-267/+253
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| * | Closes #1717. Add more precise Verilog source location information to AST and...Alberto Gonzalez2020-02-234-267/+253
* | | Merge pull request #1681 from YosysHQ/eddie/fix1663Claire Wolf2020-03-031-15/+13
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