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* Fixed handling of "input foo; reg [0:0] foo;"Clifford Wolf2015-01-151-0/+7
* Consolidate "Blocking assignment to memory.." msgs for the same lineClifford Wolf2015-01-151-3/+9
* Fixed memory->start_offset handlingClifford Wolf2015-01-011-6/+7
* Added global yosys_celltypesClifford Wolf2014-12-291-1/+1
* dict/pool changes in astClifford Wolf2014-12-293-16/+24
* Changed more code to dict<> and pool<>Clifford Wolf2014-12-283-6/+6
* Fixed mem2reg warning messageClifford Wolf2014-12-271-3/+3
* Added Yosys::{dict,nodict,vector} container typesClifford Wolf2014-12-262-2/+2
* Renamed extend() to extend_xx(), changed most users to extend_u0()Clifford Wolf2014-12-241-1/+1
* Added log_warning() APIClifford Wolf2014-11-092-10/+10
* AST simplifier: optimize constant AST_CASE nodes before recursively descendingClifford Wolf2014-10-291-31/+35
* Improvements in $readmem[bh] implementationClifford Wolf2014-10-261-8/+13
* Added support for $readmemh/$readmembClifford Wolf2014-10-262-0/+113
* Fixed constant "cond ? string1 : string2" with strings of different sizeClifford Wolf2014-10-251-0/+2
* minor indenting correctionsClifford Wolf2014-10-191-2/+2
* Builds on Mac 10.9.2 with LLVM 3.5.Parviz Palangpour2014-10-191-0/+5
* Fixed various VS warningsClifford Wolf2014-10-181-1/+1
* Wrapped math in int constructorWilliam Speirs2014-10-171-1/+1
* Fixed handling of invalid array access in mem2reg codeClifford Wolf2014-10-162-3/+15
* Do not the 'z' modifier in format string (another win32 fix)Clifford Wolf2014-10-111-2/+2
* Renamed SIZE() to GetSize() because of name collision on Win32Clifford Wolf2014-10-103-20/+20
* namespace YosysClifford Wolf2014-09-271-0/+8
* Another $clog2 bugfixClifford Wolf2014-09-081-0/+2
* Fixed $clog2 (off by one error)Clifford Wolf2014-09-061-2/+2
* Fixed assignment of out-of bounds array elementClifford Wolf2014-09-061-2/+26
* Corrected spelling mistakes found by lintianRuben Undheim2014-09-061-1/+1
* Removed $bu0 cell typeClifford Wolf2014-09-041-5/+5
* Added emscripten (emcc) support to build system and some build fixesClifford Wolf2014-08-222-1/+17
* Archibald Rust and Clifford Wolf: ffi-based dpi_call()Clifford Wolf2014-08-221-6/+90
* Fixed small memory leak in ast simplifyClifford Wolf2014-08-211-3/+3
* Added support for DPI function with different names in C and VerilogClifford Wolf2014-08-211-4/+4
* Added AstNode::asInt()Clifford Wolf2014-08-213-2/+24
* Fixed memory leak in DPI function callsClifford Wolf2014-08-211-0/+4
* Added Verilog/AST support for DPI functions (dpi_call() still unimplemented)Clifford Wolf2014-08-216-2/+81
* Added support for global tasks and functionsClifford Wolf2014-08-211-12/+26
* Added "via_celltype" attribute on task/funcClifford Wolf2014-08-181-6/+69
* Added const folding of AST_CASE to AST simplifierClifford Wolf2014-08-183-1/+41
* Improved AST ProcessGenerator performanceClifford Wolf2014-08-171-3/+3
* Use stackmap<> in AST ProcessGeneratorClifford Wolf2014-08-173-24/+22
* AST ProcessGenerator: replaced subst_*_{from,to} with subst_*_mapClifford Wolf2014-08-161-41/+26
* Fixed bug in "read_verilog -ignore_redef"Clifford Wolf2014-08-151-1/+1
* Added RTLIL::SigSpec::to_sigbit_map()Clifford Wolf2014-08-141-11/+3
* Changed the AST genWidthRTLIL subst interface to use a std::mapClifford Wolf2014-08-143-21/+31
* Fixed handling of task outputsClifford Wolf2014-08-141-2/+4
* Added module->portsClifford Wolf2014-08-141-0/+1
* Added AST_MULTIRANGE (arrays with more than 1 dimension)Clifford Wolf2014-08-063-1/+62
* Improved scope resolution of local regs in Verilog+AST frontendClifford Wolf2014-08-052-7/+26
* Fixed AST handling of variables declared inside a functions main blockClifford Wolf2014-08-051-3/+3
* More bugfixes related to new RTLIL::IdStringClifford Wolf2014-08-021-7/+7
* More cleanups related to RTLIL::IdString usageClifford Wolf2014-08-021-6/+6
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