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* ast: make design available to process_module()Zachary Snow2021-03-241-8/+8
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* ast: Use better parameter serialization for paramod names.Marcelina Kościelnicka2021-03-181-2/+25
| | | | | | | | | | | | Calling log_signal is problematic for several reasons: - with recent changes, empty string is serialized as { }, which violates the "no spaces in IdString" rule - the type (plain / real / signed / string) is dropped, wrongly conflating functionally different values and potentially introducing a subtle elaboration bug Instead, use a custom simple serialization scheme.
* verilog: fix buf/not primitives with multiple outputsXiretza2021-03-171-4/+15
| | | | | | | | | | | | From IEEE1364-2005, section 7.3 buf and not gates: > These two logic gates shall have one input and one or more outputs. > The last terminal in the terminal list shall connect to the input of the > logic gate, and the other terminals shall connect to the outputs of > the logic gate. yosys does not follow this and instead interprets the first argument as the output, the second as the input and ignores the rest.
* verilog: support module scope identifiers in parametric modulesZachary Snow2021-03-161-4/+8
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* sv: allow globals in one file to depend on globals in anotherZachary Snow2021-03-122-1/+1
| | | | | | This defers the simplification of globals so that globals in one file may depend on globals in other files. Adds a simplify() call downstream because globals are appended at the end.
* verilog: disallow overriding global parametersZachary Snow2021-03-111-0/+2
| | | | | | It was previously possible to override global parameters on a per-instance basis. This could be dangerous when using positional parameter bindings, hiding oversupplied parameters.
* Merge pull request #2643 from zachjs/fix-param-no-default-logwhitequark2021-03-081-1/+1
|\ | | | | Fix param without default log line
| * Fix param without default log lineZachary Snow2021-03-071-1/+1
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* | verilog: Use proc memory writes in the frontend.Marcelina Kościelnicka2021-03-084-29/+89
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* Merge pull request #2626 from zachjs/param-no-defaultwhitequark2021-03-071-2/+27
|\ | | | | sv: support for parameters without default values
| * sv: support for parameters without default valuesZachary Snow2021-03-021-2/+27
| | | | | | | | | | | | | | | | | | - Modules with a parameter without a default value will be automatically deferred until the hierarchy pass - Allows for parameters without defaults as module items, rather than just int the `parameter_port_list`, despite being forbidden in the LRM - Check for parameters without defaults that haven't been overriden - Add location info to parameter/localparam declarations
* | Merge pull request #2632 from zachjs/width-limitwhitequark2021-03-071-0/+6
|\ \ | | | | | | verilog: impose limit on maximum expression width
| * | verilog: impose limit on maximum expression widthZachary Snow2021-03-041-0/+6
| |/ | | | | | | | | Designs with unreasonably wide expressions would previously get stuck allocating memory forever.
* / sv: fix some edge cases for unbased unsized literalsZachary Snow2021-03-062-1/+23
|/ | | | | | - Fix explicit size cast of unbased unsized literals - Fix unbased unsized literal bound directly to port - Output `is_unsized` flag in `dumpAst`
* Merge pull request #2615 from zachjs/genrtlil-conflictwhitequark2021-03-011-12/+37
|\ | | | | genrtlil: improve name conflict error messaging
| * genrtlil: improve name conflict error messagingZachary Snow2021-02-261-12/+37
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* | Implement $countones, $isunknown and $onehot{,0}Michael Singer2021-02-261-0/+28
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* | Implement $countbits functionMichael Singer2021-02-261-0/+59
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* | Extend simplify() recursion warningZachary Snow2021-02-261-1/+1
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* frontend: Make helper functions for printing locations.Marcelina Kościelnicka2021-02-234-57/+71
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* Merge pull request #2594 from zachjs/func-arg-widthwhitequark2021-02-232-10/+30
|\ | | | | verilog: fix sizing of constant args for tasks/functions
| * verilog: fix sizing of constant args for tasks/functionsZachary Snow2021-02-212-10/+30
| | | | | | | | | | | | | | | | | | | | | | | | - Simplify synthetic localparams for normal calls to update their width - This step was inadvertently removed alongside `added_mod_children` - Support redeclaration of constant function arguments - `eval_const_function` never correctly handled this, but the issue was not exposed in the existing tests until the recent change to always attempt constant function evaluation when all-const args are used - Check asserts in const_arg_loop and const_func tests - Add coverage for width mismatch error cases
* | verilog: support recursive functions using ternary expressionsZachary Snow2021-02-123-19/+119
|/ | | | | | | This adds a mechanism for marking certain portions of elaboration as occurring within unevaluated ternary branches. To enable elaboration of the overall ternary, this also adds width detection for these unelaborated function calls.
* Merge pull request #2573 from zachjs/repeat-callwhitequark2021-02-112-72/+82
|\ | | | | verilog: refactored constant function evaluation
| * verilog: refactored constant function evaluationZachary Snow2021-02-042-72/+82
| | | | | | | | | | | | | | | | | | | | | | Elaboration now attempts constant evaluation of any function call with only constant arguments, regardless of the context or contents of the function. This removes the concept of "recommended constant evaluation" which previously applied to functions with `for` loops or which were (sometimes erroneously) identified as recursive. Any function call in a constant context (e.g., `localparam`) or which contains a constant-only procedural construct (`while` or `repeat`) in its body will fail as before if constant evaluation does not succeed.
* | genrtlil: fix signed port connection codegen failuresZachary Snow2021-02-051-1/+5
|/ | | | | | | | This fixes binding signed memory reads, signed unary expressions, and signed complex SigSpecs to ports. This also sets `is_signed` for wires generated from signed params when -pwires is used. Though not necessary for any of the current usages, `is_signed` is now appropriately set when the `extendWidth` helper is used.
* Merge pull request #2529 from zachjs/unnamed-genblkwhitequark2021-02-042-131/+141
|\ | | | | verilog: significant block scoping improvements
| * verilog: significant block scoping improvementsZachary Snow2021-01-312-131/+141
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This change set contains a number of bug fixes and improvements related to scoping and resolution in generate and procedural blocks. While many of the frontend changes are interdependent, it may be possible bring the techmap changes in under a separate PR. Declarations within unnamed generate blocks previously encountered issues because the data declarations were left un-prefixed, breaking proper scoping. The LRM outlines behavior for generating names for unnamed generate blocks. The original goal was to add this implicit labelling, but doing so exposed a number of issues downstream. Additional testing highlighted other closely related scope resolution issues, which have been fixed. This change also adds support for block item declarations within unnamed blocks in SystemVerilog mode. 1. Unlabled generate blocks are now implicitly named according to the LRM in `label_genblks`, which is invoked at the beginning of module elaboration 2. The Verilog parser no longer wraps explicitly named generate blocks in a synthetic unnamed generate block to avoid creating extra hierarchy levels where they should not exist 3. The techmap phase now allows special control identifiers to be used outside of the topmost scope, which is necessary because such wires and cells often appear in unlabeled generate blocks, which now prefix the declarations within 4. Some techlibs required modifications because they relied on the previous invalid scope resolution behavior 5. `expand_genblock` has been simplified, now only expanding the outermost scope, completely deferring the inspection and elaboration of nested scopes; names are now resolved by looking in the innermost scope and stepping outward 6. Loop variables now always become localparams during unrolling, allowing them to be resolved and shadowed like any other identifier 7. Identifiers in synthetic function call scopes are now prefixed and resolved in largely the same manner as other blocks before: `$func$\func_01$tests/simple/scopes.blk.v:60$5$\blk\x` after: `\func_01$func$tests/simple/scopes.v:60$5.blk.x` 8. Support identifiers referencing a local generate scope nested more than 1 level deep, i.e. `B.C.x` while within generate scope `A`, or using a prefix of a current or parent scope, i.e. `B.C.D.x` while in `A.B`, `A.B.C`, or `A.B.C.D` 9. Variables can now be declared within unnamed blocks in SystemVerilog mode Addresses the following issues: 656, 2423, 2493
* | ast: fix dump_vlog display of casex/casezMarcelina Kościelnicka2021-01-291-2/+2
|/ | | | | | The first child of AST_CASE is the case expression, it's subsequent childrean that are AST_COND* and can be used to discriminate the type of the case.
* dpi: Support for chandle typeDavid Shah2021-01-231-1/+16
| | | | Signed-off-by: David Shah <dave@ds0.me>
* Fix input/output attributes when resolving typedef of wireKamil Rakoczy2021-01-181-0/+3
| | | | Signed-off-by: Kamil Rakoczy <krakoczy@antmicro.com>
* verilog: improved support for recursive functionsZachary Snow2020-12-312-8/+28
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* Fix elaboration of whole memory words used as indicesZachary Snow2020-12-261-1/+8
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* Fix constants bound to redeclared function argsZachary Snow2020-12-261-5/+16
| | | | | | | | The changes in #2476 ensured that function inputs like `input x;` retained their single-bit size when instantiated with a constant argument and turned into a localparam. That change did not handle the possibility for an input to be redeclared later on with an explicit width, such as `integer x;`.
* Merge pull request #2501 from zachjs/genrtlil-tern-signwhitequark2020-12-231-0/+1
|\ | | | | genrtlil: fix mux2rtlil generated wire signedness
| * genrtlil: fix mux2rtlil generated wire signednessZachary Snow2020-12-221-0/+1
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* | Merge pull request #2476 from zachjs/const-arg-widthwhitequark2020-12-231-0/+8
|\ \ | |/ |/| Fix constants bound to single bit arguments (fixes #2383)
| * Fix constants bound to single bit arguments (fixes #2383)Zachary Snow2020-12-221-0/+8
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* | Merge pull request #2479 from zachjs/const-arg-hintwhitequark2020-12-221-0/+5
|\ \ | | | | | | Allow constant function calls in constant function arguments
| * | Allow constant function calls in constant function argumentsZachary Snow2020-12-071-0/+5
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* / Sign extend port connections where necessaryZachary Snow2020-12-181-2/+24
|/ | | | | | | | | | | - Signed cell outputs are sign extended when bound to larger wires - Signed connections are sign extended when bound to larger cell inputs - Sign extension is performed in hierarchy and flatten phases - genrtlil indirects signed constants through signed wires - Other phases producing RTLIL may need to be updated to preserve signedness information - Resolves #1418 - Resolves #2265
* Return correct modname when found in cache.Julius Roob2020-11-261-0/+1
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* Merge pull request #2378 from udif/pr_dollar_high_lowclairexen2020-10-013-31/+98
|\ | | | | Added $high(), $low(), $left(), $right()
| * We can now handle array slices (e.g. $size(x[1]) etc. )Udi Finkelstein2020-09-171-7/+6
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| * Fixed comments, removed debug messageUdi Finkelstein2020-09-161-5/+5
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| * Added $high(), $low(), $left(), $right()Udi Finkelstein2020-09-153-30/+98
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* | Merge pull request #2330 from antmicro/arrays-fix-multirange-accessclairexen2020-09-171-1/+1
|\ \ | |/ |/| Fix unsupported subarray access detection
| * Fix subarray access conditionLukasz Dalek2020-08-031-1/+1
| | | | | | | | Signed-off-by: Lukasz Dalek <ldalek@antmicro.com>
* | Merge pull request #2352 from zachjs/const-func-localparamclairexen2020-09-011-0/+12
|\ \ | | | | | | Allow localparams in constant functions
| * | Allow localparams in constant functionsZachary Snow2020-08-201-0/+12
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