iCE40/yosys - [no description]

	Commit message (Expand)	Author	Age	Files	Lines
*	Merge pull request #2025 from YosysHQ/eddie/frontend_cleanup	Eddie Hung	2020-05-05	2	-13/+13
\|\
\| *	frontend: cleanup to use more ID::*, more dict<> instead of map<>	Eddie Hung	2020-05-04	2	-13/+13
* \|	verilog: set src attribute for primitives	Eddie Hung	2020-05-04	1	-1/+3
\|/
*	Merge pull request #1996 from boqwxp/rtlil_source_locations	Eddie Hung	2020-05-04	1	-13/+13
\|\
\| *	frontend: Include complete source location instead of just `location.first_li...	Alberto Gonzalez	2020-05-01	1	-13/+13
* \|	Clear current_scope when done with RTLIL generation, fixes #1837	Claire Wolf	2020-04-22	1	-0/+4
\|/
*	ilang, ast: Store parameter order and default value information.	Marcelina Kościelnicka	2020-04-21	2	-3/+4
*	Merge pull request #1851 from YosysHQ/claire/bitselwrite	Claire Wolf	2020-04-21	4	-15/+207
\|\
\| *	Make mask-and-shift the default for bitselwrite	Claire Wolf	2020-04-16	1	-1/+1
\| *	Add LookaheadRewriter for proper bitselwrite support	Claire Wolf	2020-04-16	4	-4/+144
\| *	Improved rewrite code for writing to bit slice (disabled for now)	Claire Wolf	2020-04-15	1	-12/+64
* \|	Merge pull request #1961 from whitequark/paramod-original-name	whitequark	2020-04-21	1	-0/+3
\|\ \
\| * \|	ast, rpc: record original name of $paramod\* as \hdlname attribute.	whitequark	2020-04-18	1	-0/+3
* \| \|	Extend support for format strings in Verilog front-end	Claire Wolf	2020-04-18	1	-8/+38
\|/ /
* /	ast: Fix handling of identifiers in the global scope	David Shah	2020-04-16	2	-2/+7
\|/
*	Merge pull request #1918 from whitequark/simplify-improve_enum	whitequark	2020-04-15	1	-5/+3
\|\
\| *	ast/simplify: improve enum handling.	whitequark	2020-04-15	1	-5/+3
* \|	Fix 5bba9c3, closes #1876	Claire Wolf	2020-04-14	1	-7/+13
* \|	Merge pull request #1879 from jjj11x/jjj11x/package_decl	whitequark	2020-04-14	1	-0/+23
\|\ \
\| * \|	support using previously declared types/localparams/params in package	Jeff Wang	2020-04-07	1	-0/+23
\| \|/
* /	duplicated enum item names should result in an error	Jeff Wang	2020-04-07	1	-2/+3
\|/
*	Merge pull request #1853 from YosysHQ/eddie/fix_dynslice	Eddie Hung	2020-04-02	1	-1/+2
\|\
\| *	ast: cap dynamic range select to size of signal, suppresses warnings	Eddie Hung	2020-04-01	1	-1/+2
* \|	kernel: big fat patch to use more ID::, otherwise ID()	Eddie Hung	2020-04-02	3	-182/+170
* \|	kernel: use more ID::*	Eddie Hung	2020-04-02	3	-53/+53
* \|	Merge pull request #1845 from YosysHQ/eddie/kernel_speedup	Eddie Hung	2020-04-02	2	-37/+43
\|\ \
\| * \|	kernel: more pass by const ref, more speedups	Eddie Hung	2020-03-18	2	-37/+43
* \| \|	Merge pull request #1848 from YosysHQ/eddie/fix_dynslice	Claire Wolf	2020-04-01	1	-1/+1
\|\ \ \ \| \| \|/ \| \|/\|
\| * \|	ast: simplify to fully populate dynamic slicing case transformation	Eddie Hung	2020-03-31	1	-1/+1
\| \|/
* \|	Merge pull request #1783 from boqwxp/astcc_cleanup	Eddie Hung	2020-03-30	1	-13/+20
\|\ \
\| * \|	Add explanatory comment about inefficient wire removal and remove superfluous...	Alberto Gonzalez	2020-03-30	1	-4/+8
\| * \|	Revert over-aggressive change to a more modest cleanup.	Alberto Gonzalez	2020-03-27	1	-2/+3
\| * \|	Clean up pseudo-private member usage in `frontends/ast/ast.cc`.	Alberto Gonzalez	2020-03-19	1	-11/+13
\| \|/
* \|	Merge pull request #1607 from whitequark/simplify-simplify-meminit	Claire Wolf	2020-03-27	1	-63/+82
\|\ \
\| * \|	ast: avoid intermediate wires/assigns when lowering to AST_MEMINIT.	whitequark	2020-02-07	1	-65/+84
* \| \|	Simplify was not being called for packages. Broke typedef enums.	Peter Crozier	2020-03-22	1	-5/+8
* \| \|	Fix NDEBUG warnings	Eddie Hung	2020-03-19	1	-1/+1
* \| \|	Add precise locations for asserts	huaixv	2020-03-19	1	-0/+1
\| \|/ \|/\|
* \|	Merge pull request #1718 from boqwxp/precise_locations	Claire Wolf	2020-03-03	4	-267/+253
\|\ \
\| * \|	Closes #1717. Add more precise Verilog source location information to AST and...	Alberto Gonzalez	2020-02-23	4	-267/+253
* \| \|	Merge pull request #1681 from YosysHQ/eddie/fix1663	Claire Wolf	2020-03-03	1	-15/+13
\|\ \ \
\| * \| \|	verilog: instead of modifying localparam size, extend init constant expr	Eddie Hung	2020-02-05	1	-15/+13
\| \| \|/ \| \|/\|
* \| \|	Merge pull request #1724 from YosysHQ/eddie/abc9_specify	Eddie Hung	2020-03-02	2	-12/+20
\|\ \ \
\| * \| \|	ast: quiet down when deriving blackbox modules	Eddie Hung	2020-02-27	2	-12/+20
\| \| \|/ \| \|/\|
* \| \|	ast: fixes #1710; do not generate RTLIL for unreachable ternary	Eddie Hung	2020-02-27	1	-9/+22
* \| \|	Comment out log()	Eddie Hung	2020-02-27	1	-1/+1
\|/ /
* \|	Merge pull request #1703 from YosysHQ/eddie/specify_improve	Eddie Hung	2020-02-21	1	-7/+11
\|\ \
\| * \|	verilog: fix $specify3 check	Eddie Hung	2020-02-13	1	-7/+11
* \| \|	Merge pull request #1642 from jjj11x/jjj11x/sv-enum	Claire Wolf	2020-02-20	4	-16/+221
\|\ \ \ \| \|/ / \|/\| \|
\| * \|	remove unnecessary blank line	Jeff Wang	2020-02-17	1	-2/+1