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* Encode filename unprintable charsMiodrag Milanovic2022-08-082-26/+26
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* verilog: fix width/sign detection for functionsZachary Snow2022-05-301-5/+7
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* verilog: fix size and signedness of array querying functionsJannis Harder2022-05-302-3/+2
| | | | | | | | | | genrtlil.cc and simplify.cc had inconsistent and slightly broken handling of signedness for array querying functions. These functions are defined to return a signed result. Simplify always produced an unsigned and genrtlil always a signed 32-bit result ignoring the context. Includes tests for the the relvant edge cases for context dependent conversions.
* verilog: fix $past's signednessJannis Harder2022-05-252-1/+2
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* verilog: fix signedness when removing unreachable casesJannis Harder2022-05-241-0/+1
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* sv: fix always_comb auto nosync for nested and function blocksZachary Snow2022-04-051-1/+11
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* Fix access to whole sub-structs (#3086)Kamil Rakoczy2022-02-142-6/+18
| | | | | | * Add support for accessing whole struct * Update tests Signed-off-by: Kamil Rakoczy <krakoczy@antmicro.com>
* verilog: fix dynamic dynamic range asgn elabZachary Snow2022-02-111-17/+34
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* verilog: fix const func eval with upto variablesZachary Snow2022-02-112-3/+11
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* fix dumpAst() compilation warningZachary Snow2022-01-181-1/+1
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* sv: auto add nosync to certain always_comb local varsZachary Snow2022-01-071-0/+127
| | | | | If a local variable is always assigned before it is used, then adding nosync prevents latches from being needlessly generated.
* sv: fix size cast internal expression extensionZachary Snow2022-01-071-2/+9
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* sv: fix size cast clipping expression widthZachary Snow2022-01-031-1/+2
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* fix width detection of array querying function in case and case item expressionsZachary Snow2021-12-172-2/+5
| | | | | I also removed the unnecessary shadowing of `width_hint` and `sign_hint` in the corresponding case in `simplify()`.
* Support parameters using struct as a wiretype (#3050)Kamil Rakoczy2021-11-161-7/+23
| | | Signed-off-by: Kamil Rakoczy <krakoczy@antmicro.com>
* genrtlil: Fix displaying debug info in packagesKamil Rakoczy2021-11-101-1/+2
| | | | Signed-off-by: Kamil Rakoczy <krakoczy@antmicro.com>
* verilog: use derived module info to elaborate cell connectionsZachary Snow2021-10-254-41/+291
| | | | | | | | - Attempt to lookup a derived module if it potentially contains a port connection with elaboration ambiguities - Mark the cell if module has not yet been derived - This can be extended to implement automatic hierarchical port connections in a future change
* Split out logic for reprocessing an AstModuleRupert Swarbrick2021-10-252-24/+57
| | | | | This will enable other features to use same core logic for replacing an existing AstModule with a newly elaborated version.
* verilog: fix multiple AST_PREFIX scope resolution issuesZachary Snow2021-09-211-4/+9
| | | | | | | | - Root AST_PREFIX nodes are now subject to genblk expansion to allow them to refer to a locally-visible generate block - Part selects on AST_PREFIX member leafs can now refer to generate block items (previously would not resolve and raise an error) - Add source location information to AST_PREFIX nodes
* Generate an RTLIL representation of bind constructsRupert Swarbrick2021-08-136-2/+193
| | | | | | | | | | | | | | | | | | | | | | | | | This code now takes the AST nodes of type AST_BIND and generates a representation in the RTLIL for them. This is a little tricky, because a binding of the form: bind baz foo_t foo_i (.arg (1 + bar)); means "make an instance of foo_t called foo_i, instantiate it inside baz and connect the port arg to the result of the expression 1+bar". Of course, 1+bar needs a cell for the addition. Where should that cell live? With this patch, the Binding structure that represents the construct is itself an AST::AstModule module. This lets us put the adder cell inside it. We'll pull the contents out and plonk them into 'baz' when we actually do the binding operation as part of the hierarchy pass. Of course, we don't want RTLIL::Binding to contain an AST::AstModule (since kernel code shouldn't depend on a frontend), so we define RTLIL::Binding as an abstract base class and put the AST-specific code into an AST::Binding subclass. This is analogous to the AST::AstModule class.
* genrtlil: add width detection for AST_PREFIX nodesZachary Snow2021-07-291-0/+8
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* verilog: Emit $meminit_v2 cell.Marcelina Kościelnicka2021-07-284-51/+83
| | | | Fixes #2447.
* Add support for parsing the SystemVerilog 'bind' constructRupert Swarbrick2021-07-163-1/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This doesn't do anything useful yet: the patch just adds support for the syntax to the lexer and parser and adds some tests to check the syntax parses properly. This generates AST nodes, but doesn't yet generate RTLIL. Since our existing hierarchical_identifier parser doesn't allow bit selects (so you can't do something like foo[1].bar[2].baz), I've also not added support for a trailing bit select (the "constant_bit_select" non-terminal in "bind_target_instance" in the spec). If we turn out to need this in future, we'll want to augment hierarchical_identifier and its other users too. Note that you can't easily use the BNF from the spec: bind_directive ::= "bind" bind_target_scope [ : bind_target_instance_list] bind_instantiation ; | "bind" bind_target_instance bind_instantiation ; even if you fix the lookahead problem, because code like this matches both branches in the BNF: bind a b b_i (.*); The problem is that 'a' could either be a module name or a degenerate hierarchical reference. This seems to be a genuine syntactic ambiguity, which the spec resolves (p739) by saying that we have to wait until resolution time (the hierarchy pass) and take whatever is defined, treating 'a' as an instance name if it names both an instance and a module. To keep the parser simple, it currently accepts this invalid syntax: bind a.b : c d e (.*); This is invalid because we're in the first branch of the BNF above, so the "a.b" term should match bind_target_scope: a module or interface identifier, not an arbitrary hierarchical identifier. This will fail in the hierarchy pass (when it's implemented in a future patch).
* sv: fix two struct access bugsZachary Snow2021-07-153-1/+10
| | | | | - preserve signedness of struct members - fix initial width detection of struct members (e.g., in case expressions)
* rtlil: Make Process handling more uniform with Cell and Wire.Marcelina Kościelnicka2021-07-121-3/+1
| | | | | | - add a backlink to module from Process - make constructor and destructor protected, expose Module functions to add and remove processes
* sv: fix a few struct and enum memory leaksZachary Snow2021-07-061-0/+7
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* ast: delete wires and localparams after finishing const evaluationXiretza2021-06-141-0/+8
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* verilog: fix leaking ASTNodesXiretza2021-06-141-0/+5
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* ast: fix error condition causing assert to failXiretza2021-06-141-2/+1
| | | | | type2str returns a string that doesn't start with $ or \, so it can't be assigned to an IdString.
* Merge pull request #2817 from YosysHQ/claire/fixemailsClaire Xen2021-06-095-5/+5
|\ | | | | Fixing old e-mail addresses and deadnames
| * Fixing old e-mail addresses and deadnamesClaire Xenia Wolf2021-06-085-5/+5
| | | | | | | | | | | | | | | | s/((Claire|Xen|Xenia|Clifford)\s+)+(Wolf|Xen)\s+<(claire|clifford)@(symbioticeda.com|clifford.at|yosyshq.com)>/Claire Xenia Wolf <claire@yosyshq.com>/gi; s/((Nina|Nak|N\.)\s+)+Engelhardt\s+<nak@(symbioticeda.com|yosyshq.com)>/N. Engelhardt <nak@yosyshq.com>/gi; s/((David)\s+)+Shah\s+<(dave|david)@(symbioticeda.com|yosyshq.com|ds0.me)>/David Shah <dave@ds0.me>/gi; s/((Miodrag)\s+)+Milanovic\s+<(miodrag|micko)@(symbioticeda.com|yosyshq.com)>/Miodrag Milanovic <micko@yosyshq.com>/gi; s,https?://www.clifford.at/yosys/,http://yosyshq.net/yosys/,g;
* | verilog: check for module scope identifiers during width detectionZachary Snow2021-06-083-13/+30
| | | | | | | | | | | | | | | | The recent fix for case expression width detection causes the width of the expressions to be queried before they are simplified. Because the logic supporting module scope identifiers only existed in simplify, looking them up would fail during width detection. This moves the logic to a common helper used in both simplify() and detectSignWidthWorker().
* | mem2reg: tolerate out of bounds constant accessesZachary Snow2021-06-081-5/+42
|/ | | | This brings the mem2reg behavior in line with the nomem2reg behavior.
* sv: support tasks and functions within packagesZachary Snow2021-06-012-1/+21
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* verilog: fix case expression sign and width handlingZachary Snow2021-05-253-12/+49
| | | | | | | | | - The case expression and case item expressions are extended to the maximum width among them, and are only interpreted as signed if all of them are signed - Add overall width and sign detection for AST_CASE - Add sign argument to genWidthRTLIL helper - Coverage for both const and non-const case statements
* Change the type of current_module to ModuleRupert Swarbrick2021-05-132-24/+26
| | | | | | | | | | | The current_module global is needed so that genRTLIL has somewhere to put cells and wires that it generates as it makes sense of expressions that it sees. However, that doesn't actually need to be an AstModule: the Module base class is enough. This patch should cause no functional change, but the point is that it's now possible to call genRTLIL with a module that isn't an AstModule as "current_module". This will be needed for 'bind' support.
* Use range-based for loop in AST::processRupert Swarbrick2021-05-131-21/+21
| | | | | | No functional change: just get rid of the explicit iterator and replace (*it)-> with child->. It's even the same number of characters, but is hopefully a little easier to read.
* ast: make design available to process_module()Zachary Snow2021-03-241-8/+8
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* ast: Use better parameter serialization for paramod names.Marcelina Kościelnicka2021-03-181-2/+25
| | | | | | | | | | | | Calling log_signal is problematic for several reasons: - with recent changes, empty string is serialized as { }, which violates the "no spaces in IdString" rule - the type (plain / real / signed / string) is dropped, wrongly conflating functionally different values and potentially introducing a subtle elaboration bug Instead, use a custom simple serialization scheme.
* verilog: fix buf/not primitives with multiple outputsXiretza2021-03-171-4/+15
| | | | | | | | | | | | From IEEE1364-2005, section 7.3 buf and not gates: > These two logic gates shall have one input and one or more outputs. > The last terminal in the terminal list shall connect to the input of the > logic gate, and the other terminals shall connect to the outputs of > the logic gate. yosys does not follow this and instead interprets the first argument as the output, the second as the input and ignores the rest.
* verilog: support module scope identifiers in parametric modulesZachary Snow2021-03-161-4/+8
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* sv: allow globals in one file to depend on globals in anotherZachary Snow2021-03-122-1/+1
| | | | | | This defers the simplification of globals so that globals in one file may depend on globals in other files. Adds a simplify() call downstream because globals are appended at the end.
* verilog: disallow overriding global parametersZachary Snow2021-03-111-0/+2
| | | | | | It was previously possible to override global parameters on a per-instance basis. This could be dangerous when using positional parameter bindings, hiding oversupplied parameters.
* Merge pull request #2643 from zachjs/fix-param-no-default-logwhitequark2021-03-081-1/+1
|\ | | | | Fix param without default log line
| * Fix param without default log lineZachary Snow2021-03-071-1/+1
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* | verilog: Use proc memory writes in the frontend.Marcelina Kościelnicka2021-03-084-29/+89
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* Merge pull request #2626 from zachjs/param-no-defaultwhitequark2021-03-071-2/+27
|\ | | | | sv: support for parameters without default values
| * sv: support for parameters without default valuesZachary Snow2021-03-021-2/+27
| | | | | | | | | | | | | | | | | | - Modules with a parameter without a default value will be automatically deferred until the hierarchy pass - Allows for parameters without defaults as module items, rather than just int the `parameter_port_list`, despite being forbidden in the LRM - Check for parameters without defaults that haven't been overriden - Add location info to parameter/localparam declarations
* | Merge pull request #2632 from zachjs/width-limitwhitequark2021-03-071-0/+6
|\ \ | | | | | | verilog: impose limit on maximum expression width
| * | verilog: impose limit on maximum expression widthZachary Snow2021-03-041-0/+6
| |/ | | | | | | | | Designs with unreasonably wide expressions would previously get stuck allocating memory forever.
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