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* Added $global_clock verilog syntax support for creating $ff cellsClifford Wolf2016-10-141-4/+11
* Added $past, $stable, $rose, $fell SVA functionsClifford Wolf2016-09-192-2/+141
* Added assertpmuxClifford Wolf2016-09-071-0/+1
* Avoid creation of bogus initial blocks for assert/assume in always @*Clifford Wolf2016-09-063-1/+13
* Added $anyconst support to yosys-smtbmcClifford Wolf2016-08-301-0/+2
* Removed $aconst cell typeClifford Wolf2016-08-302-5/+5
* Removed $predict againClifford Wolf2016-08-284-6/+2
* Fixed bug with memories that do not have a down-to-zero data widthClifford Wolf2016-08-221-2/+13
* Another bugfix in mem2reg codeClifford Wolf2016-08-213-7/+31
* Minor improvements to AstNode::dumpAst() and AstNode::dumpVlog()Clifford Wolf2016-08-211-4/+15
* Fixed finish_addr handling in $readmemh/$readmembClifford Wolf2016-08-201-3/+3
* Optimize memory address port width in wreduce and memory_collect, not verilog...Clifford Wolf2016-08-192-4/+13
* Only allow posedge/negedge with 1 bit wide signalsClifford Wolf2016-08-101-0/+2
* Added $anyconst and $aconstClifford Wolf2016-07-272-0/+49
* Added "read_verilog -dump_rtlil"Clifford Wolf2016-07-272-8/+21
* Using $initstate in "initial assume" and "initial assert"Clifford Wolf2016-07-211-1/+6
* Added $initstate cell type and vlog functionClifford Wolf2016-07-211-0/+24
* After reading the SV spec, using non-standard predict() instead of expect()Clifford Wolf2016-07-214-6/+6
* Added basic support for $expect cellsClifford Wolf2016-07-134-7/+16
* Fixed mem assignment in left-hand-side concatenationClifford Wolf2016-07-081-0/+44
* A few modifications after pull request commentsRuben Undheim2016-06-181-2/+2
* Added support for SystemVerilog packages with localparam definitionsRuben Undheim2016-06-183-1/+16
* Fixed procedural assignments to non-unique lvalues, e.g. {y,y} = {a,b}Clifford Wolf2016-05-271-0/+11
* Fixed access-after-delete bug in mem2reg codeClifford Wolf2016-05-272-6/+23
* fixed typos in error messagesClifford Wolf2016-05-271-3/+3
* Include <cmath> in yosys.hClifford Wolf2016-05-081-9/+0
* Added "yosys -D" featureClifford Wolf2016-04-211-1/+1
* Fixed handling of parameters and const functions in casex/casez patternClifford Wolf2016-04-214-6/+31
* Do not set "nosync" on task outputs, fixes #134Clifford Wolf2016-03-241-1/+2
* Added support for $stop system taskClifford Wolf2016-03-211-5/+5
* Added $display %m support, fixed mem leak in $display, fixes #128Clifford Wolf2016-03-191-20/+44
* Fixed localparam signdness, fixes #127Clifford Wolf2016-03-181-1/+1
* Set "nosync" attribute on internal task/function wiresClifford Wolf2016-03-181-0/+1
* Fixed some visual studio warningsClifford Wolf2016-02-133-4/+4
* genrtlil: avoid converting SigSpec to set<SigBit> when going through removeSi...Rick Altherr2016-01-311-3/+3
* Fixed handling of re-declarations of wires in tasks and functionsClifford Wolf2015-11-231-7/+26
* More bugfixes in handling of parameters in tasks and functionsClifford Wolf2015-11-121-1/+11
* Fixed handling of parameters and localparams in functionsClifford Wolf2015-11-112-3/+8
* Import more std:: stuff into Yosys namespaceClifford Wolf2015-10-252-32/+32
* Fixed complexity of assigning to vectors in constant functionsClifford Wolf2015-10-011-0/+3
* Fixed detection of unconditional $readmem[hb]Clifford Wolf2015-09-301-4/+11
* Bugfixes in $readmem[hb]Clifford Wolf2015-09-251-4/+7
* Fixed segfault in AstNode::asRealClifford Wolf2015-09-251-1/+1
* Added read-enable to memory modelClifford Wolf2015-09-251-0/+1
* Fixed AstNode::mkconst_bits() segfault on zero-sized constantClifford Wolf2015-09-241-1/+1
* Bugfix in handling of multi-dimensional memoriesClifford Wolf2015-09-231-2/+2
* Warning for $display/$write outside initial blockClifford Wolf2015-09-231-7/+8
* Fixed multi-level prefix resolvingClifford Wolf2015-09-221-0/+2
* Improvements to $display system taskAndrew Zonenberg2015-09-191-9/+22
* Added AST_INITIAL checks for $finish and $displayClifford Wolf2015-09-181-2/+9