| Commit message (Collapse) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | Properly construct $live and $fair cells from "if (...) assume/assert ↵ | Clifford Wolf | 2019-09-02 | 1 | -7/+18 |
| | | | | | | | | | (s_eventually ...)" Fixes https://github.com/YosysHQ/SymbiYosys/issues/59 Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
| * | Do not propagate mem2reg attribute through to result | Eddie Hung | 2019-08-22 | 1 | -1/+2 |
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| * | mem2reg to preserve user attributes and src | Eddie Hung | 2019-08-21 | 1 | -0/+4 |
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| * | substr() -> compare() | Eddie Hung | 2019-08-07 | 1 | -3/+3 |
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| * | Merge remote-tracking branch 'origin/master' into eddie/cleanup | Eddie Hung | 2019-08-07 | 1 | -15/+2 |
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| | * | Fix handling of functions/tasks without top-level begin-end block, fixes #1231 | Clifford Wolf | 2019-08-06 | 1 | -15/+2 |
| | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
| * | | IdString::str().substr() -> IdString::substr() | Eddie Hung | 2019-08-06 | 1 | -1/+1 |
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| * | Merge branch 'master' of github.com:YosysHQ/yosys into clifford/fix968 | Clifford Wolf | 2019-05-06 | 1 | -0/+1 |
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| | * | Add splitcmplxassign test case and silence splitcmplxassign warning | Clifford Wolf | 2019-05-01 | 1 | -0/+1 |
| | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
| * | | Re-enable "final loop assignment" feature | Clifford Wolf | 2019-05-01 | 1 | -2/+0 |
| |/ | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
| * | Disabled "final loop assignment" feature | Clifford Wolf | 2019-04-30 | 1 | -0/+2 |
| | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
| * | Add final loop variable assignment when unrolling for-loops, fixes #968 | Clifford Wolf | 2019-04-30 | 1 | -0/+7 |
| | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
| * | Determine correct signedness and expression width in for loop unrolling, ↵ | Clifford Wolf | 2019-04-22 | 1 | -3/+18 |
| | | | | | | | fixes #370 Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
| * | support repeat loops with constant repeat counts outside of constant functions | Zachary Snow | 2019-04-09 | 1 | -1/+20 |
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| * | Fix mem2reg handling of memories with upto data ports, fixes #888 | Clifford Wolf | 2019-03-21 | 1 | -1/+10 |
| | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
| * | fix local name resolution in prefix constructs | Zachary Snow | 2019-03-18 | 1 | -1/+5 |
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| * | Improve handling of memories used in mem index expressions on LHS of an ↵ | Clifford Wolf | 2019-03-12 | 1 | -5/+16 |
| | | | | | | | assignment Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
| * | Remove outdated "blocking assignment to memory" warning | Clifford Wolf | 2019-03-12 | 1 | -10/+0 |
| | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
| * | Only set MEM2REG_FL_CONST_LHS/MEM2REG_FL_VAR_LHS for non-init writes, fixes #867 | Clifford Wolf | 2019-03-12 | 1 | -6/+8 |
| | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
| * | Merge pull request #858 from YosysHQ/clifford/svalabels | Clifford Wolf | 2019-03-09 | 1 | -0/+1 |
| |\ | | | | | Add support for using SVA labels in yosys-smtbmc console output | ||||
| | * | Add support for SVA labels in read_verilog | Clifford Wolf | 2019-03-07 | 1 | -0/+1 |
| | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
| * | | Fix handling of task output ports in clocked always blocks, fixes #857 | Clifford Wolf | 2019-03-07 | 1 | -15/+18 |
| |/ | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
| * | Only run derive on blackbox modules when ports have dynamic size | Clifford Wolf | 2019-03-02 | 1 | -0/+19 |
| | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
| * | Fix $global_clock handling vs autowire | Clifford Wolf | 2019-03-02 | 1 | -1/+1 |
| | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
| * | Fix $readmem[hb] for mem2reg memories, fixes #785 | Clifford Wolf | 2019-03-02 | 1 | -0/+35 |
| | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
| * | Use mem2reg on memories that only have constant-index write ports | Clifford Wolf | 2019-03-01 | 1 | -0/+11 |
| | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
| * | Fix handling of defparam for when default_nettype is none | Clifford Wolf | 2019-02-24 | 1 | -0/+4 |
| | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
| * | Fixes related to handling of autowires and upto-ranges, fixes #814 | Clifford Wolf | 2019-02-21 | 1 | -7/+10 |
| | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
| * | Fix handling of expression width in $past, fixes #810 | Clifford Wolf | 2019-02-21 | 1 | -1/+1 |
| | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
| * | Fix segfault in AST simplify | Clifford Wolf | 2018-12-18 | 1 | -0/+5 |
| | | | | | | | (as proposed by Dan Gisselquist) Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
| * | Make return value of $clog2 signed | Sylvain Munaut | 2018-11-24 | 1 | -1/+1 |
| | | | | | | | | | As per Verilog 2005 - 17.11.1. Fixes #708 Signed-off-by: Sylvain Munaut <tnt@246tNt.com> | ||||
| * | Various indenting fixes in AST front-end (mostly space vs tab issues) | Clifford Wolf | 2018-11-04 | 1 | -38/+33 |
| | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
| * | Make and dependent upon LSB only | ZipCPU | 2018-11-03 | 1 | -2/+8 |
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| * | Do not generate "reg assigned in a continuous assignment" warnings for "rand ↵ | Clifford Wolf | 2018-11-01 | 1 | -2/+15 |
| | | | | | | | reg" Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
| * | Merge pull request #659 from rubund/sv_interfaces | Clifford Wolf | 2018-10-18 | 1 | -1/+1 |
| |\ | | | | | Support for SystemVerilog interfaces and modports | ||||
| | * | Synthesis support for SystemVerilog interfaces | Ruben Undheim | 2018-10-12 | 1 | -1/+1 |
| | | | | | | | | | This time doing the changes mostly in AST before RTLIL generation | ||||
| * | | Merge pull request #638 from udif/pr_reg_wire_error | Clifford Wolf | 2018-10-17 | 1 | -0/+12 |
| |\ \ | |/ |/| | Fix issue #630 | ||||
| | * | Fixed issue #630 by fixing a minor typo in the previous commit | Udi Finkelstein | 2018-09-25 | 1 | -2/+2 |
| | | | | | | | | | (as well as a non critical minor code optimization) | ||||
| | * | Merge branch 'master' into pr_reg_wire_error | Udi Finkelstein | 2018-09-18 | 1 | -123/+121 |
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| | * | | Fixed remaining cases where we check fo wire reg/wire incorrect assignments | Udi Finkelstein | 2018-09-18 | 1 | -0/+12 |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | on Yosys-generated assignments. In this case, offending code was: module top(input in, output out); function func; input arg; func = arg; endfunction assign out = func(in); endmodule | ||||
| * | | | Add read_verilog $changed support | Dan Gisselquist | 2018-10-01 | 1 | -1/+4 |
| | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
| * | | | Fix handling of $past 2nd argument in read_verilog | Clifford Wolf | 2018-09-30 | 1 | -1/+1 |
| | |/ |/| | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
| * | | Merge pull request #590 from hzeller/remaining-file-error | Clifford Wolf | 2018-08-15 | 1 | -15/+15 |
| |\ \ | | | | | | | Fix remaining log_file_error(); emit dependent file references in new… | ||||
| | * | | Fix remaining log_file_error(); emit dependent file references in new line. | Henner Zeller | 2018-07-20 | 1 | -15/+15 |
| | | | | | | | | | | | | | | | | | | | | | | There are some places that reference dependent file locations ("this function was called from ..."). These are now in a separate line for ease of jumping to it with the editor (behaves similarly to compilers that emit dependent messages). | ||||
| * | | | Merge pull request #513 from udif/pr_reg_wire_error | Clifford Wolf | 2018-08-15 | 1 | -0/+42 |
| |\ \ \ | |/ / |/| / | |/ | Add error checking for reg/wire/logic misuse - PR now passes 'make test' (plus a new test) | ||||
| | * | Modified errors into warnings | Udi Finkelstein | 2018-06-05 | 1 | -6/+38 |
| | | | | | | | | | No longer false warnings for memories and assertions | ||||
| | * | This PR should be the base for discussion, do not merge it yet! | Udi Finkelstein | 2018-03-11 | 1 | -0/+10 |
| | | | | | | | | | | | | | | | | | | | | | | | | | It correctly detects reg/wire mix and incorrect use on blocking,nonblocking assignments within blocks and assign statements. What it DOES'T do: Detect registers connected to output ports of instances. Where it FAILS: memorty nonblocking assignments causes spurious (I assume??) errors on yosys-generated "_ADDR", "_DATA", "EN" signals. You can test it with tests/simple/reg_wire_error.v (look inside for the comments to enable/disable specific lines) | ||||
| * | | Convert more log_error() to log_file_error() where possible. | Henner Zeller | 2018-07-20 | 1 | -54/+53 |
| | | | | | | | | | | | Mostly statements that span over multiple lines and haven't been caught with the previous conversion. | ||||
| * | | Use log_file_warning(), log_file_error() functions. | Henner Zeller | 2018-07-20 | 1 | -61/+60 |
| |/ | | | | Wherever we can report a source-level location. | ||||
| * | Add $allconst and $allseq cell types | Clifford Wolf | 2018-02-23 | 1 | -1/+1 |
| | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
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index : iCE40/yosys | |
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