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| author | Ruben Undheim <ruben.undheim@gmail.com> | 2018-10-11 23:33:31 +0200 |
|---|---|---|
| committer | Ruben Undheim <ruben.undheim@gmail.com> | 2018-10-12 21:11:36 +0200 |
| commit | 75009ada3c2a4bcd38c52c8fb871c9e8c1f2e6b1 (patch) | |
| tree | e8d3be5d6134dbf4fc26b47f9481f80a4bdfc4c7 /frontends/ast/simplify.cc | |
| parent | 9850de405a11fe93e4562c86be0a0830b83c2785 (diff) | |
| download | yosys-75009ada3c2a4bcd38c52c8fb871c9e8c1f2e6b1.tar.gz yosys-75009ada3c2a4bcd38c52c8fb871c9e8c1f2e6b1.tar.bz2 yosys-75009ada3c2a4bcd38c52c8fb871c9e8c1f2e6b1.zip | |
Synthesis support for SystemVerilog interfaces
This time doing the changes mostly in AST before RTLIL generation
Diffstat (limited to 'frontends/ast/simplify.cc')
| -rw-r--r-- | frontends/ast/simplify.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/frontends/ast/simplify.cc b/frontends/ast/simplify.cc index 71eba547c..2a561ea5f 100644 --- a/frontends/ast/simplify.cc +++ b/frontends/ast/simplify.cc @@ -71,7 +71,7 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage, if (stage == 0) { - log_assert(type == AST_MODULE); + log_assert(type == AST_MODULE || type == AST_INTERFACE); last_blocking_assignment_warn = pair<string, int>(); deep_recursion_warning = true; |