| Commit message (Expand) | Author | Age | Files | Lines |
|---|
| ... | |
| * | Removed $aconst cell type | Clifford Wolf | 2016-08-30 | 1 | -3/+3 |
| * | Removed $predict again | Clifford Wolf | 2016-08-28 | 1 | -2/+0 |
| * | Another bugfix in mem2reg code | Clifford Wolf | 2016-08-21 | 1 | -0/+2 |
| * | Optimize memory address port width in wreduce and memory_collect, not verilog... | Clifford Wolf | 2016-08-19 | 1 | -4/+8 |
| * | Only allow posedge/negedge with 1 bit wide signals | Clifford Wolf | 2016-08-10 | 1 | -0/+2 |
| * | Added $anyconst and $aconst | Clifford Wolf | 2016-07-27 | 1 | -0/+45 |
| * | After reading the SV spec, using non-standard predict() instead of expect() | Clifford Wolf | 2016-07-21 | 1 | -2/+2 |
| * | Added basic support for $expect cells | Clifford Wolf | 2016-07-13 | 1 | -2/+7 |
| * | Added support for SystemVerilog packages with localparam definitions | Ruben Undheim | 2016-06-18 | 1 | -0/+1 |
| * | Fixed procedural assignments to non-unique lvalues, e.g. {y,y} = {a,b} | Clifford Wolf | 2016-05-27 | 1 | -0/+11 |
| * | fixed typos in error messages | Clifford Wolf | 2016-05-27 | 1 | -3/+3 |
| * | Fixed handling of parameters and const functions in casex/casez pattern | Clifford Wolf | 2016-04-21 | 1 | -2/+4 |
| * | Fixed some visual studio warnings | Clifford Wolf | 2016-02-13 | 1 | -1/+1 |
| * | genrtlil: avoid converting SigSpec to set<SigBit> when going through removeSi... | Rick Altherr | 2016-01-31 | 1 | -3/+3 |
| * | Fixed handling of parameters and localparams in functions | Clifford Wolf | 2015-11-11 | 1 | -0/+5 |
| * | Import more std:: stuff into Yosys namespace | Clifford Wolf | 2015-10-25 | 1 | -20/+20 |
| * | Added read-enable to memory model | Clifford Wolf | 2015-09-25 | 1 | -0/+1 |
| * | Spell check (by Larry Doolittle) | Clifford Wolf | 2015-08-14 | 1 | -7/+7 |
| * | Added WORDS parameter to $meminit | Clifford Wolf | 2015-07-31 | 1 | -1/+9 |
| * | Fixed trailing whitespaces | Clifford Wolf | 2015-07-02 | 1 | -2/+2 |
| * | Const-fold parameter defs on-demand in AstNode::detectSignWidthWorker() | Clifford Wolf | 2015-03-01 | 1 | -2/+4 |
| * | Added non-std verilog assume() statement | Clifford Wolf | 2015-02-26 | 1 | -4/+7 |
| * | Convert floating point cell parameters to strings | Clifford Wolf | 2015-02-18 | 1 | -9/+12 |
| * | Various fixes for memories with offsets | Clifford Wolf | 2015-02-14 | 1 | -6/+4 |
| * | Creating $meminit cells in verilog front-end | Clifford Wolf | 2015-02-14 | 1 | -6/+9 |
| * | Ignore explicit assignments to constants in HDL code | Clifford Wolf | 2015-02-08 | 1 | -0/+14 |
| * | Fixed a bug with autowire bit size | Clifford Wolf | 2015-02-08 | 1 | -9/+3 |
| * | Fixed memory->start_offset handling | Clifford Wolf | 2015-01-01 | 1 | -6/+7 |
| * | Changed more code to dict<> and pool<> | Clifford Wolf | 2014-12-28 | 1 | -3/+3 |
| * | Renamed extend() to extend_xx(), changed most users to extend_u0() | Clifford Wolf | 2014-12-24 | 1 | -1/+1 |
| * | Added log_warning() API | Clifford Wolf | 2014-11-09 | 1 | -6/+6 |
| * | Renamed SIZE() to GetSize() because of name collision on Win32 | Clifford Wolf | 2014-10-10 | 1 | -8/+8 |
| * | Fixed assignment of out-of bounds array element | Clifford Wolf | 2014-09-06 | 1 | -2/+26 |
| * | Removed $bu0 cell type | Clifford Wolf | 2014-09-04 | 1 | -5/+5 |
| * | Added Verilog/AST support for DPI functions (dpi_call() still unimplemented) | Clifford Wolf | 2014-08-21 | 1 | -0/+1 |
| * | Improved AST ProcessGenerator performance | Clifford Wolf | 2014-08-17 | 1 | -3/+3 |
| * | Use stackmap<> in AST ProcessGenerator | Clifford Wolf | 2014-08-17 | 1 | -21/+19 |
| * | AST ProcessGenerator: replaced subst_*_{from,to} with subst_*_map | Clifford Wolf | 2014-08-16 | 1 | -41/+26 |
| * | Added RTLIL::SigSpec::to_sigbit_map() | Clifford Wolf | 2014-08-14 | 1 | -11/+3 |
| * | Changed the AST genWidthRTLIL subst interface to use a std::map | Clifford Wolf | 2014-08-14 | 1 | -17/+27 |
| * | More cleanups related to RTLIL::IdString usage | Clifford Wolf | 2014-08-02 | 1 | -6/+6 |
| * | Renamed port access function on RTLIL::Cell, added param access functions | Clifford Wolf | 2014-07-31 | 1 | -22/+22 |
| * | Moved some stuff to kernel/yosys.{h,cc}, using Yosys:: namespace | Clifford Wolf | 2014-07-31 | 1 | -10/+14 |
| * | Added $shift and $shiftx cell types (needed for correct part select behavior) | Clifford Wolf | 2014-07-29 | 1 | -5/+11 |
| * | Removed left over debug code | Clifford Wolf | 2014-07-28 | 1 | -1/+0 |
| * | Fixed part selects of parameters | Clifford Wolf | 2014-07-28 | 1 | -5/+10 |
| * | Set results of out-of-bounds static bit/part select to undef | Clifford Wolf | 2014-07-28 | 1 | -5/+31 |
| * | Fixed RTLIL code generator for part select of parameter | Clifford Wolf | 2014-07-28 | 1 | -2/+2 |
| * | Fixed width detection for part selects | Clifford Wolf | 2014-07-28 | 1 | -2/+2 |
| * | Added support for "upto" wires to Verilog front- and back-end | Clifford Wolf | 2014-07-28 | 1 | -11/+8 |
