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| author | Clifford Wolf <clifford@clifford.at> | 2015-09-25 12:23:11 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2015-09-25 12:23:11 +0200 |
| commit | 924d9d6e86a5e9a2294479345daac1c03d78008a (patch) | |
| tree | 04d28a2068b32c44c0aca2b8b815f6fc51cec427 /frontends/ast/genrtlil.cc | |
| parent | ec92c8965960fa814c3663e987bc2a7eb80965e5 (diff) | |
| download | yosys-924d9d6e86a5e9a2294479345daac1c03d78008a.tar.gz yosys-924d9d6e86a5e9a2294479345daac1c03d78008a.tar.bz2 yosys-924d9d6e86a5e9a2294479345daac1c03d78008a.zip | |
Added read-enable to memory model
Diffstat (limited to 'frontends/ast/genrtlil.cc')
| -rw-r--r-- | frontends/ast/genrtlil.cc | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/frontends/ast/genrtlil.cc b/frontends/ast/genrtlil.cc index a2655e9a5..c322faf7b 100644 --- a/frontends/ast/genrtlil.cc +++ b/frontends/ast/genrtlil.cc @@ -1220,6 +1220,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint) id2ast->meminfo(mem_width, mem_size, addr_bits); cell->setPort("\\CLK", RTLIL::SigSpec(RTLIL::State::Sx, 1)); + cell->setPort("\\EN", RTLIL::SigSpec(RTLIL::State::Sx, 1)); cell->setPort("\\ADDR", children[0]->genWidthRTLIL(addr_bits)); cell->setPort("\\DATA", RTLIL::SigSpec(wire)); |