iCE40/yosys - [no description]

	Commit message (Expand)	Author	Age	Files	Lines
*	Use only module->addCell() and module->remove() to create and delete cells	Clifford Wolf	2014-07-25	1	-54/+19
*	Replaced more old SigChunk programming patterns	Clifford Wolf	2014-07-24	1	-7/+7
*	Removed RTLIL::SigSpec::optimize()	Clifford Wolf	2014-07-23	1	-11/+0
*	SigSpec refactoring: More cleanups of old SigSpec use pattern	Clifford Wolf	2014-07-22	1	-3/+6
*	SigSpec refactoring: change RTLIL::SigSpec::chunks() to be read-only, created...	Clifford Wolf	2014-07-22	1	-1/+1
*	SigSpec refactoring: change RTLIL::SigSpec::size() to be read-only	Clifford Wolf	2014-07-22	1	-55/+11
*	SigSpec refactoring: using the accessor functions everywhere	Clifford Wolf	2014-07-22	1	-60/+60
*	SigSpec refactoring: renamed chunks and width to __chunks and __width	Clifford Wolf	2014-07-22	1	-60/+60
*	changes in verilog frontend for new $mem/$memwr WR_EN interface	Clifford Wolf	2014-07-16	1	-3/+0
*	More found_real-related fixes to AstNode::detectSignWidthWorker	Clifford Wolf	2014-06-24	1	-6/+6
*	fixed signdness detection for expressions with reals	Clifford Wolf	2014-06-21	1	-2/+8
*	Added found_real feature to AstNode::detectSignWidth	Clifford Wolf	2014-06-16	1	-4/+9
*	improved (fixed) conversion of real values to bit vectors	Clifford Wolf	2014-06-14	1	-4/+4
*	Added real->int convertion in ast genrtlil	Clifford Wolf	2014-06-14	1	-0/+12
*	further improved const function support	Clifford Wolf	2014-06-07	1	-5/+5
*	improved const function support	Clifford Wolf	2014-06-06	1	-1/+1
*	Fixed bit-extending in $mux argument (use $bu0 instead of $pos)	Clifford Wolf	2014-02-26	1	-5/+5
*	Don't blow up constants unneccessarily in Verilog frontend	Clifford Wolf	2014-02-24	1	-1/+1
*	Added Verilog support for "`default_nettype none"	Clifford Wolf	2014-02-17	1	-1/+4
*	Correctly convert constants to RTLIL (fixed undef handling)	Clifford Wolf	2014-02-15	1	-11/+1
*	Created basic support for function calls in parameter values	Clifford Wolf	2014-02-14	1	-6/+6
*	Added TRANSPARENT parameter to $memrd (and RD_TRANSPARENT to $mem)	Clifford Wolf	2014-02-03	1	-0/+1
*	Added constant size expression support of sized constants	Clifford Wolf	2014-02-01	1	-0/+8
*	Added read_verilog -icells option	Clifford Wolf	2014-01-29	1	-0/+2
*	Added $assert cell	Clifford Wolf	2014-01-19	1	-0/+32
*	Added correct handling of $memwr priority	Clifford Wolf	2014-01-03	1	-0/+2
*	Added support for non-const === and !== (for miter circuits)	Clifford Wolf	2013-12-27	1	-2/+2
*	Added proper === and !== support in constant expressions	Clifford Wolf	2013-12-27	1	-6/+10
*	Various improvements in support for generate statements	Clifford Wolf	2013-12-04	1	-0/+1
*	Replaced signed_parameters API with CONST_FLAG_SIGNED	Clifford Wolf	2013-12-04	1	-4/+0
*	Replaced RTLIL::Const::str with generic decoder method	Clifford Wolf	2013-12-04	1	-22/+11
*	Added support for local regs in named blocks	Clifford Wolf	2013-12-04	1	-0/+4
*	Fixed temp net name generation in rtlil process generator for abbreviated nam...	Clifford Wolf	2013-11-28	1	-0/+2
*	Added "src" attribute to processes	Clifford Wolf	2013-11-28	1	-0/+1
*	Added module->avail_parameters (for advanced techmap features)	Clifford Wolf	2013-11-24	1	-1/+5
*	Remove auto_wire framework (smarter than the verilog standard)	Clifford Wolf	2013-11-24	1	-9/+1
*	Implemented correct handling of signed module parameters	Clifford Wolf	2013-11-24	1	-0/+4
*	Major improvements in mem2reg and added "init" sync rules	Clifford Wolf	2013-11-21	1	-4/+29
*	Fixed parsing of default cases when not last case	Clifford Wolf	2013-11-18	1	-12/+16
*	Cleanups and bugfixes in response to new internal cell checker	Clifford Wolf	2013-11-11	1	-3/+6
*	More undef-propagation related fixes	Clifford Wolf	2013-11-08	1	-0/+4
*	Fixed handling of power operator	Clifford Wolf	2013-11-07	1	-8/+20
*	Fixed more extend vs. extend_u0 issues	Clifford Wolf	2013-11-07	1	-2/+2
*	Renamed extend_un0() to extend_u0() and use it in genrtlil	Clifford Wolf	2013-11-07	1	-4/+8
*	Fixed const folding in corner cases with parameters	Clifford Wolf	2013-11-07	1	-4/+7
*	Fixed width detection for replicate operator	Clifford Wolf	2013-11-07	1	-0/+1
*	Various fixes for correct parameter support	Clifford Wolf	2013-11-07	1	-12/+22
*	Fixed the fix for propagation of width hints for $signed() and $unsigned()	Clifford Wolf	2013-11-07	1	-5/+4
*	Fixed propagation of width hints for $signed() and $unsigned()	Clifford Wolf	2013-11-06	1	-1/+4
*	Additional fixes for undef propagation in concat and replicate ops	Clifford Wolf	2013-11-06	1	-0/+4