iCE40/yosys - [no description]

	Commit message (Collapse)	Author	Age	Files	Lines
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*	further improved const function support	Clifford Wolf	2014-06-07	1	-1/+1
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*	improved const function support	Clifford Wolf	2014-06-06	1	-0/+1
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*	added while and repeat support to verilog parser	Clifford Wolf	2014-06-06	1	-0/+1
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*	Added Verilog support for "`default_nettype none"	Clifford Wolf	2014-02-17	1	-3/+3
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*	Added support for FOR loops in function calls in parameters	Clifford Wolf	2014-02-14	1	-0/+1
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*	Created basic support for function calls in parameter values	Clifford Wolf	2014-02-14	1	-1/+6
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*	Implemented read_verilog -defer	Clifford Wolf	2014-02-13	1	-1/+1
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*	Added constant size expression support of sized constants	Clifford Wolf	2014-02-01	1	-0/+1
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*	Added read_verilog -icells option	Clifford Wolf	2014-01-29	1	-3/+3
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*	Fixed algorithmic complexity of AST simplification of long expressions	Clifford Wolf	2014-01-20	1	-0/+3
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*	Added Verilog parser support for asserts	Clifford Wolf	2014-01-19	1	-0/+1
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*	Added proper === and !== support in constant expressions	Clifford Wolf	2013-12-27	1	-0/+2
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*	Keep strings as strings in const ternary and concat	Clifford Wolf	2013-12-05	1	-1/+2
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*	Added AstNode::mkconst_str API	Clifford Wolf	2013-12-05	1	-0/+1
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*	Various improvements in support for generate statements	Clifford Wolf	2013-12-04	1	-0/+2
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*	Replaced signed_parameters API with CONST_FLAG_SIGNED	Clifford Wolf	2013-12-04	1	-1/+1
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*	Replaced RTLIL::Const::str with generic decoder method	Clifford Wolf	2013-12-04	1	-0/+2
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*	Added verilog frontend -ignore_redef option	Clifford Wolf	2013-11-24	1	-1/+1
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*	Remove auto_wire framework (smarter than the verilog standard)	Clifford Wolf	2013-11-24	1	-4/+2
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*	Implemented correct handling of signed module parameters	Clifford Wolf	2013-11-24	1	-1/+1
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*	Major improvements in mem2reg and added "init" sync rules	Clifford Wolf	2013-11-21	1	-1/+20
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*	Various ast changes for early expression width detection (prep for constfold ↵	Clifford Wolf	2013-11-02	1	-1/+5
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*	Fixed handling of boolean attributes (frontends)	Clifford Wolf	2013-10-24	1	-0/+1
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*	Improved ast dumping (ast/verilog frontend)	Clifford Wolf	2013-08-19	1	-3/+3
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*	Added "design" command (-reset, -save, -load)	Clifford Wolf	2013-07-27	1	-0/+1
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*	Major redesign of expr width/sign detecion (verilog/ast frontend)	Clifford Wolf	2013-07-09	1	-1/+5
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*	Added defparam support to Verilog/AST frontend	Clifford Wolf	2013-07-04	1	-0/+1
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*	Enabled AST/Verilog front-end optimizations per default	Clifford Wolf	2013-06-10	1	-3/+3
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*	Now only use value from "initial" when no matching "always" block is found	Clifford Wolf	2013-03-31	1	-1/+1
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*	Added AST_INITIAL (before verilog "initial" was mapped to AST_ALWAYS)	Clifford Wolf	2013-03-31	1	-0/+1
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*	Implemented proper handling of stub placeholder modules	Clifford Wolf	2013-03-28	1	-3/+3
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*	Added nosync attribute and some async reset related fixes	Clifford Wolf	2013-03-25	1	-1/+1
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*	Added mem2reg option to verilog frontend	Clifford Wolf	2013-03-24	1	-4/+4
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*	Improved mem2reg handling in ast simplifier	Clifford Wolf	2013-03-24	1	-1/+1
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*	Added support for verilog genblock[index].member syntax	Clifford Wolf	2013-02-26	1	-0/+1
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*	initial import	Clifford Wolf	2013-01-05	1	-0/+228