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author | Clifford Wolf <clifford@clifford.at> | 2013-11-24 17:29:11 +0100 |
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committer | Clifford Wolf <clifford@clifford.at> | 2013-11-24 17:29:11 +0100 |
commit | f71e27dbf15d063ca45378ff2eb2d8102220f199 (patch) | |
tree | 67137e2ddf4dcf588fa4397d15d3e7648805a896 /frontends/ast/ast.h | |
parent | 609caa23b5e12547c043dc4a1827d1a531af1992 (diff) | |
download | yosys-f71e27dbf15d063ca45378ff2eb2d8102220f199.tar.gz yosys-f71e27dbf15d063ca45378ff2eb2d8102220f199.tar.bz2 yosys-f71e27dbf15d063ca45378ff2eb2d8102220f199.zip |
Remove auto_wire framework (smarter than the verilog standard)
Diffstat (limited to 'frontends/ast/ast.h')
-rw-r--r-- | frontends/ast/ast.h | 6 |
1 files changed, 2 insertions, 4 deletions
diff --git a/frontends/ast/ast.h b/frontends/ast/ast.h index f9f47f6a4..349832256 100644 --- a/frontends/ast/ast.h +++ b/frontends/ast/ast.h @@ -228,7 +228,6 @@ namespace AST bool nolatches, nomem2reg, mem2reg, lib, noopt; virtual ~AstModule(); virtual RTLIL::IdString derive(RTLIL::Design *design, std::map<RTLIL::IdString, RTLIL::Const> parameters, std::set<RTLIL::IdString> signed_parameters); - virtual void update_auto_wires(std::map<RTLIL::IdString, int> auto_sizes); virtual RTLIL::Module *clone() const; }; @@ -239,9 +238,8 @@ namespace AST extern void (*set_line_num)(int); extern int (*get_line_num)(); - // set set_line_num and get_line_num to internal dummy functions - // (done by simplify(), AstModule::derive and AstModule::update_auto_wires to control - // the filename and linenum properties of new nodes not generated by a frontend parser) + // set set_line_num and get_line_num to internal dummy functions (done by simplify() and AstModule::derive + // to control the filename and linenum properties of new nodes not generated by a frontend parser) void use_internal_line_num(); } |