iCE40/yosys - [no description]

	Commit message (Expand)	Author	Age	Files	Lines
*	Cleanups in handling of read_verilog -defer and -icells	Clifford Wolf	2014-02-20	1	-6/+7
*	Added Verilog support for "`default_nettype none"	Clifford Wolf	2014-02-17	1	-2/+6
*	Added support for FOR loops in function calls in parameters	Clifford Wolf	2014-02-14	1	-0/+1
*	Created basic support for function calls in parameter values	Clifford Wolf	2014-02-14	1	-1/+1
*	Implemented read_verilog -defer	Clifford Wolf	2014-02-13	1	-57/+78
*	Added constant size expression support of sized constants	Clifford Wolf	2014-02-01	1	-0/+1
*	Added read_verilog -icells option	Clifford Wolf	2014-01-29	1	-2/+6
*	Fixed algorithmic complexity of AST simplification of long expressions	Clifford Wolf	2014-01-20	1	-0/+1
*	Added Verilog parser support for asserts	Clifford Wolf	2014-01-19	1	-0/+1
*	Added proper === and !== support in constant expressions	Clifford Wolf	2013-12-27	1	-0/+4
*	Keep strings as strings in const ternary and concat	Clifford Wolf	2013-12-05	1	-1/+13
*	Added AstNode::mkconst_str API	Clifford Wolf	2013-12-05	1	-0/+17
*	Various improvements in support for generate statements	Clifford Wolf	2013-12-04	1	-0/+10
*	Replaced signed_parameters API with CONST_FLAG_SIGNED	Clifford Wolf	2013-12-04	1	-2/+2
*	Replaced RTLIL::Const::str with generic decoder method	Clifford Wolf	2013-12-04	1	-2/+24
*	Added verilog frontend -ignore_redef option	Clifford Wolf	2013-11-24	1	-3/+8
*	Remove auto_wire framework (smarter than the verilog standard)	Clifford Wolf	2013-11-24	1	-38/+0
*	Implemented correct handling of signed module parameters	Clifford Wolf	2013-11-24	1	-2/+2
*	Renamed "placeholder" to "blackbox"	Clifford Wolf	2013-11-22	1	-1/+1
*	Added dumping of attributes in AST frontend	Clifford Wolf	2013-11-18	1	-0/+11
*	Call internal checker more often	Clifford Wolf	2013-11-10	1	-0/+1
*	Various fixes for correct parameter support	Clifford Wolf	2013-11-07	1	-2/+2
*	Various ast changes for early expression width detection (prep for constfold ...	Clifford Wolf	2013-11-02	1	-6/+26
*	Fixed handling of boolean attributes (frontends)	Clifford Wolf	2013-10-24	1	-1/+15
*	Improved ast dumping (ast/verilog frontend)	Clifford Wolf	2013-08-19	1	-48/+20
*	Added "design" command (-reset, -save, -load)	Clifford Wolf	2013-07-27	1	-0/+15
*	Fixed AST_CONSTANT node generation	Clifford Wolf	2013-07-07	1	-1/+1
*	Added defparam support to Verilog/AST frontend	Clifford Wolf	2013-07-04	1	-1/+2
*	Enabled AST/Verilog front-end optimizations per default	Clifford Wolf	2013-06-10	1	-3/+7
*	Added log_assert() api	Clifford Wolf	2013-05-24	1	-2/+1
*	Fixed handling of positional module parameters	Clifford Wolf	2013-04-26	1	-6/+4
*	Only use sha1 checksums for names of parametric modules when the verbose form...	Clifford Wolf	2013-04-26	1	-9/+20
*	Now only use value from "initial" when no matching "always" block is found	Clifford Wolf	2013-03-31	1	-1/+15
*	Added AST_INITIAL (before verilog "initial" was mapped to AST_ALWAYS)	Clifford Wolf	2013-03-31	1	-0/+9
*	Implemented proper handling of stub placeholder modules	Clifford Wolf	2013-03-28	1	-2/+18
*	Added mem2reg option to verilog frontend	Clifford Wolf	2013-03-24	1	-2/+6
*	Moved stand-alone libs to libs/ directory and added libs/subcircuit	Clifford Wolf	2013-02-27	1	-1/+1
*	Added support for verilog genblock[index].member syntax	Clifford Wolf	2013-02-26	1	-0/+1
*	initial import	Clifford Wolf	2013-01-05	1	-0/+859