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Author
Age
Files
Lines
*
Added emscripten (emcc) support to build system and some build fixes
Clifford Wolf
2014-08-22
1
-0
/
+4
*
Added AstNode::asInt()
Clifford Wolf
2014-08-21
1
-1
/
+22
*
Added Verilog/AST support for DPI functions (dpi_call() still unimplemented)
Clifford Wolf
2014-08-21
1
-0
/
+1
*
Added support for global tasks and functions
Clifford Wolf
2014-08-21
1
-12
/
+26
*
Added const folding of AST_CASE to AST simplifier
Clifford Wolf
2014-08-18
1
-0
/
+8
*
Use stackmap<> in AST ProcessGenerator
Clifford Wolf
2014-08-17
1
-1
/
+1
*
Fixed bug in "read_verilog -ignore_redef"
Clifford Wolf
2014-08-15
1
-1
/
+1
*
Changed the AST genWidthRTLIL subst interface to use a std::map
Clifford Wolf
2014-08-14
1
-2
/
+1
*
Added module->ports
Clifford Wolf
2014-08-14
1
-0
/
+1
*
Added AST_MULTIRANGE (arrays with more than 1 dimension)
Clifford Wolf
2014-08-06
1
-0
/
+7
*
Preparations for RTLIL::IdString redesign: cleanup of existing code
Clifford Wolf
2014-08-02
1
-2
/
+2
*
Replaced sha1 implementation
Clifford Wolf
2014-08-01
1
-27
/
+2
*
Added module->design and cell->module, wire->module pointers
Clifford Wolf
2014-07-31
1
-5
/
+5
*
Moved some stuff to kernel/yosys.{h,cc}, using Yosys:: namespace
Clifford Wolf
2014-07-31
1
-1
/
+5
*
Added support for "upto" wires to Verilog front- and back-end
Clifford Wolf
2014-07-28
1
-1
/
+4
*
Using log_assert() instead of assert()
Clifford Wolf
2014-07-28
1
-2
/
+2
*
Added proper Design->addModule interface
Clifford Wolf
2014-07-27
1
-0
/
+1
*
Refactoring: Renamed RTLIL::Design::modules to modules_
Clifford Wolf
2014-07-27
1
-5
/
+5
*
Use undef (x/z vs. NaN) rules for real values from IEEE Std 1800-2012
Clifford Wolf
2014-06-16
1
-0
/
+2
*
Improved AstNode::realAsConst for large numbers
Clifford Wolf
2014-06-15
1
-1
/
+1
*
Improved AstNode::asReal for large integers
Clifford Wolf
2014-06-15
1
-9
/
+12
*
improved (fixed) conversion of real values to bit vectors
Clifford Wolf
2014-06-14
1
-0
/
+18
*
Added handling of real-valued parameters/localparams
Clifford Wolf
2014-06-14
1
-4
/
+9
*
Implemented basic real arithmetic
Clifford Wolf
2014-06-14
1
-1
/
+30
*
Added Verilog lexer and parser support for real values
Clifford Wolf
2014-06-13
1
-0
/
+5
*
Add support for cell arrays
Clifford Wolf
2014-06-07
1
-0
/
+1
*
added while and repeat support to verilog parser
Clifford Wolf
2014-06-06
1
-0
/
+1
*
Include id2ast pointers when dumping AST
Clifford Wolf
2014-03-05
1
-0
/
+6
*
Cleanups in handling of read_verilog -defer and -icells
Clifford Wolf
2014-02-20
1
-6
/
+7
*
Added Verilog support for "`default_nettype none"
Clifford Wolf
2014-02-17
1
-2
/
+6
*
Added support for FOR loops in function calls in parameters
Clifford Wolf
2014-02-14
1
-0
/
+1
*
Created basic support for function calls in parameter values
Clifford Wolf
2014-02-14
1
-1
/
+1
*
Implemented read_verilog -defer
Clifford Wolf
2014-02-13
1
-57
/
+78
*
Added constant size expression support of sized constants
Clifford Wolf
2014-02-01
1
-0
/
+1
*
Added read_verilog -icells option
Clifford Wolf
2014-01-29
1
-2
/
+6
*
Fixed algorithmic complexity of AST simplification of long expressions
Clifford Wolf
2014-01-20
1
-0
/
+1
*
Added Verilog parser support for asserts
Clifford Wolf
2014-01-19
1
-0
/
+1
*
Added proper === and !== support in constant expressions
Clifford Wolf
2013-12-27
1
-0
/
+4
*
Keep strings as strings in const ternary and concat
Clifford Wolf
2013-12-05
1
-1
/
+13
*
Added AstNode::mkconst_str API
Clifford Wolf
2013-12-05
1
-0
/
+17
*
Various improvements in support for generate statements
Clifford Wolf
2013-12-04
1
-0
/
+10
*
Replaced signed_parameters API with CONST_FLAG_SIGNED
Clifford Wolf
2013-12-04
1
-2
/
+2
*
Replaced RTLIL::Const::str with generic decoder method
Clifford Wolf
2013-12-04
1
-2
/
+24
*
Added verilog frontend -ignore_redef option
Clifford Wolf
2013-11-24
1
-3
/
+8
*
Remove auto_wire framework (smarter than the verilog standard)
Clifford Wolf
2013-11-24
1
-38
/
+0
*
Implemented correct handling of signed module parameters
Clifford Wolf
2013-11-24
1
-2
/
+2
*
Renamed "placeholder" to "blackbox"
Clifford Wolf
2013-11-22
1
-1
/
+1
*
Added dumping of attributes in AST frontend
Clifford Wolf
2013-11-18
1
-0
/
+11
*
Call internal checker more often
Clifford Wolf
2013-11-10
1
-0
/
+1
*
Various fixes for correct parameter support
Clifford Wolf
2013-11-07
1
-2
/
+2
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