| Commit message (Collapse) | Author | Age | Files | Lines | ||
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| * | | read_aiger: new naming fixes | Eddie Hung | 2019-02-20 | 1 | -5/+5 | |
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| * | | read_aiger to name wires with internal name, less likely to clash | Eddie Hung | 2019-02-20 | 1 | -18/+15 | |
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| * | | Same for ascii AIGERs too | Eddie Hung | 2019-02-19 | 1 | -6/+13 | |
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| * | | read_aiger to cope with non-unique POs | Eddie Hung | 2019-02-19 | 1 | -6/+13 | |
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| * | | read_aiger to create sane $lut names, and rename when renaming driving wire | Eddie Hung | 2019-02-19 | 1 | -2/+11 | |
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| * | | Add comment | Eddie Hung | 2019-02-19 | 1 | -1/+2 | |
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| * | | Get rid of boost dep, fix the FIXMEs for Win32? | Eddie Hung | 2019-02-19 | 1 | -14/+14 | |
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| * | | In read_xaiger, do not construct ConstEval for every LUT | Eddie Hung | 2019-02-16 | 1 | -1/+1 | |
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| * | | read_aiger to ignore output = input of same wire; also create new output for ↵ | Eddie Hung | 2019-02-16 | 1 | -2/+16 | |
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| * | | read_aiger to disable log_debug | Eddie Hung | 2019-02-16 | 1 | -1/+2 | |
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| * | | read_xaiger() to use f.read() not readsome() | Eddie Hung | 2019-02-16 | 1 | -1/+2 | |
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| * | | read_aiger() to cope with constant outputs, mixed wideports, do cleaning | Eddie Hung | 2019-02-16 | 1 | -8/+130 | |
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| * | | read_aiger with more asserts, and call clean | Eddie Hung | 2019-02-15 | 1 | -4/+11 | |
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| * | | Leave FIXME for clean | Eddie Hung | 2019-02-13 | 1 | -3/+3 | |
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| * | | Use module->addLut() | Eddie Hung | 2019-02-13 | 1 | -5/+1 | |
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| * | | Use ConstEval to compute LUT masks | Eddie Hung | 2019-02-13 | 2 | -63/+69 | |
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| * | | Merge remote-tracking branch 'origin/read_aiger' into xaig | Eddie Hung | 2019-02-13 | 1 | -10/+3 | |
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| | * | Merge branch 'read_aiger' of github.com:eddiehung/yosys into read_aiger | Eddie Hung | 2019-02-12 | 1 | -3/+1 | |
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| | | * | Do not break for constraints | Eddie Hung | 2019-02-11 | 1 | -1/+0 | |
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| | | * | No increment line_count for binary ANDs | Eddie Hung | 2019-02-11 | 1 | -1/+1 | |
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| | | * | Do not ignore newline after AND in binary AIG | Eddie Hung | 2019-02-11 | 1 | -1/+0 | |
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| | * | | Use module->add{Not,And}Gate() functions | Eddie Hung | 2019-02-12 | 1 | -8/+2 | |
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| * | | Add support for read_aiger -wideports | Eddie Hung | 2019-02-12 | 2 | -6/+15 | |
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| * | | Add support for read_aiger -map | Eddie Hung | 2019-02-12 | 2 | -4/+82 | |
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| * | | Parse 'm' in xaiger | Eddie Hung | 2019-02-12 | 1 | -20/+57 | |
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| * | | Add read_xaiger | Eddie Hung | 2019-02-11 | 2 | -27/+108 | |
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| * | addDff -> addDffGate as per @daveshah1 | Eddie Hung | 2019-02-08 | 1 | -1/+1 | |
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| * | Fix tabulation | Eddie Hung | 2019-02-08 | 1 | -28/+28 | |
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| * | -module_name arg to go before -clk_name | Eddie Hung | 2019-02-08 | 1 | -7/+7 | |
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| * | Allow module name to be determined by argument too | Eddie Hung | 2019-02-08 | 2 | -14/+44 | |
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| * | Refactor into AigerReader class | Eddie Hung | 2019-02-08 | 2 | -79/+92 | |
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| * | Parse binary AIG files | Eddie Hung | 2019-02-08 | 1 | -49/+164 | |
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| * | Refactor to parse_aiger_header() | Eddie Hung | 2019-02-08 | 1 | -26/+32 | |
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| * | Add comment | Eddie Hung | 2019-02-08 | 1 | -0/+1 | |
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| * | Handle reset logic in latches | Eddie Hung | 2019-02-08 | 1 | -2/+17 | |
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| * | Change literal vars from int to unsigned | Eddie Hung | 2019-02-08 | 1 | -1/+1 | |
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| * | Create clk outside of latch loop | Eddie Hung | 2019-02-08 | 1 | -7/+9 | |
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| * | Handle latch symbols too | Eddie Hung | 2019-02-08 | 1 | -3/+1 | |
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| * | Remove return after log_error | Eddie Hung | 2019-02-08 | 1 | -27/+9 | |
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| * | Add support for symbol tables | Eddie Hung | 2019-02-08 | 1 | -1/+49 | |
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| * | Stub for binary AIGER | Eddie Hung | 2019-02-08 | 1 | -3/+8 | |
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| * | Refactor | Eddie Hung | 2019-02-06 | 1 | -1/+8 | |
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| * | WIP | Eddie Hung | 2019-02-06 | 3 | -0/+247 | |
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index : iCE40/yosys | |
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