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path: root/frontends/aiger/aigerparse.cc
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* Add ConstEvalAig specialised for AIGsEddie Hung2019-06-131-3/+2
* parse_xaiger to cope with inoutsEddie Hung2019-06-121-6/+0
* ConsistencyEddie Hung2019-06-121-1/+1
* Merge remote-tracking branch 'origin/master' into xaigEddie Hung2019-06-121-859/+833
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| * Fix spacing from spaces to tabsEddie Hung2019-06-071-362/+362
| * Fix spacing (entire file is wrong anyway, will fix later)Eddie Hung2019-06-071-3/+3
| * Remove unnecessary std::getline() for ASCIIEddie Hung2019-06-071-3/+0
| * Fix read_aiger -- create zero driver, fix init width, parse 'b'Eddie Hung2019-06-071-13/+51
| * Rename labelEddie Hung2019-05-211-6/+5
| * Try againEddie Hung2019-05-211-4/+10
| * Fix warningEddie Hung2019-05-211-3/+2
* | Move clean from aigerparse to abc9Eddie Hung2019-04-231-2/+0
* | Tidy upEddie Hung2019-04-221-1/+1
* | Revert "Temporarily remove 'r' extension"Eddie Hung2019-04-221-0/+18
* | Temporarily remove 'r' extensionEddie Hung2019-04-221-18/+0
* | Merge remote-tracking branch 'origin/master' into xaigEddie Hung2019-04-221-3/+0
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| * Add log_debug() frameworkClifford Wolf2019-04-221-2/+0
* | read_aiger to parse 'r' extensionEddie Hung2019-04-181-0/+18
* | Ignore a/i/o/h XAIGER extensionsEddie Hung2019-04-171-0/+7
* | Forgot backslashesEddie Hung2019-04-121-1/+1
* | Handle __dummy_o__ and __const[01]__ in read_aiger not abcEddie Hung2019-04-121-0/+4
* | Merge branch 'xaig' of github.com:YosysHQ/yosys into xaigEddie Hung2019-04-121-12/+32
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| * | Fix inout handling for -map optionEddie Hung2019-04-121-10/+30
* | | Also cope with duplicated CIsEddie Hung2019-04-121-5/+23
* | | Cope with an output having same name as an input (i.e. CO)Eddie Hung2019-04-121-5/+23
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* | parse_aiger() to rename all $lut cells after "clean"Eddie Hung2019-04-101-24/+21
* | Fix spacingEddie Hung2019-04-081-29/+29
* | parse_xaiger() to really pass single and multi-bit inout testsEddie Hung2019-02-261-10/+12
* | parse_xaiger() to cope with multi bit inoutsEddie Hung2019-02-261-0/+11
* | parse_xaiger() to untransform $inout.out output portsEddie Hung2019-02-251-5/+20
* | read_aiger to accept empty string for clk_name, passable only if no latchesEddie Hung2019-02-251-0/+2
* | read_aiger to work with symbol tableEddie Hung2019-02-211-8/+47
* | Add attributionEddie Hung2019-02-211-1/+1
* | Merge branch 'read_aiger' into xaigEddie Hung2019-02-211-2/+7
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| * Fix for using POSIX basenameEddie Hung2019-02-191-2/+4
| * Missing OSX headers?Eddie Hung2019-02-171-0/+5
| * read_aiger to ignore line after ands for ascii, not binaryEddie Hung2019-02-171-2/+1
* | read_aiger to not do -purge for cleanEddie Hung2019-02-201-1/+1
* | lut/not/and suffix to be ${lut,not,and}Eddie Hung2019-02-201-13/+13
* | read_aiger to also rename 0 index lut when wideportsEddie Hung2019-02-201-2/+14
* | read_aiger: new naming fixesEddie Hung2019-02-201-5/+5
* | read_aiger to name wires with internal name, less likely to clashEddie Hung2019-02-201-18/+15
* | Same for ascii AIGERs tooEddie Hung2019-02-191-6/+13
* | read_aiger to cope with non-unique POsEddie Hung2019-02-191-6/+13
* | read_aiger to create sane $lut names, and rename when renaming driving wireEddie Hung2019-02-191-2/+11
* | Add commentEddie Hung2019-02-191-1/+2
* | Get rid of boost dep, fix the FIXMEs for Win32?Eddie Hung2019-02-191-14/+14
* | In read_xaiger, do not construct ConstEval for every LUTEddie Hung2019-02-161-1/+1
* | read_aiger to ignore output = input of same wire; also create new output for ...Eddie Hung2019-02-161-2/+16
* | read_aiger to disable log_debugEddie Hung2019-02-161-1/+2