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path: root/frontends/aiger/aigerparse.cc
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* Fix formatting for msys2 mingw build using GetSizeMiodrag Milanovic2019-08-011-0/+4
* Fix missing semicolon in Windows-specific code in aigerparse.cc.William D. Jones2019-07-141-2/+2
* Replace log_assert() with meaningful log_error()Eddie Hung2019-06-281-1/+5
* Refactor for one "abc_carry" attribute on moduleEddie Hung2019-06-271-31/+37
* Remove unneeded includeEddie Hung2019-06-271-3/+0
* Reduce log_debug spam in parse_xaiger()Eddie Hung2019-06-211-16/+19
* Workaround issues exposed by gcc-4.8Eddie Hung2019-06-211-0/+7
* Fix broken abc9.v test due to inout being 1'bxEddie Hung2019-06-201-3/+10
* Fix issue with part of PI being 1'bxEddie Hung2019-06-201-4/+6
* CleanupEddie Hung2019-06-161-20/+1
* Cover __APPLE__ too for little to big endianEddie Hung2019-06-141-4/+7
* Further cleanup based on @daveshah1Eddie Hung2019-06-141-10/+20
* Resolve comments from @daveshah1Eddie Hung2019-06-141-2/+2
* CleanupEddie Hung2019-06-141-7/+3
* Add TODO to parse_xaigerEddie Hung2019-06-141-0/+1
* Optimise some moreEddie Hung2019-06-131-58/+53
* Move ConstEvalAig to aigerparse.ccEddie Hung2019-06-131-3/+161
* Add ConstEvalAig specialised for AIGsEddie Hung2019-06-131-3/+2
* parse_xaiger to cope with inoutsEddie Hung2019-06-121-6/+0
* ConsistencyEddie Hung2019-06-121-1/+1
* Merge remote-tracking branch 'origin/master' into xaigEddie Hung2019-06-121-859/+833
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| * Fix spacing from spaces to tabsEddie Hung2019-06-071-362/+362
| * Fix spacing (entire file is wrong anyway, will fix later)Eddie Hung2019-06-071-3/+3
| * Remove unnecessary std::getline() for ASCIIEddie Hung2019-06-071-3/+0
| * Fix read_aiger -- create zero driver, fix init width, parse 'b'Eddie Hung2019-06-071-13/+51
| * Rename labelEddie Hung2019-05-211-6/+5
| * Try againEddie Hung2019-05-211-4/+10
| * Fix warningEddie Hung2019-05-211-3/+2
* | Move clean from aigerparse to abc9Eddie Hung2019-04-231-2/+0
* | Tidy upEddie Hung2019-04-221-1/+1
* | Revert "Temporarily remove 'r' extension"Eddie Hung2019-04-221-0/+18
* | Temporarily remove 'r' extensionEddie Hung2019-04-221-18/+0
* | Merge remote-tracking branch 'origin/master' into xaigEddie Hung2019-04-221-3/+0
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| * Add log_debug() frameworkClifford Wolf2019-04-221-2/+0
* | read_aiger to parse 'r' extensionEddie Hung2019-04-181-0/+18
* | Ignore a/i/o/h XAIGER extensionsEddie Hung2019-04-171-0/+7
* | Forgot backslashesEddie Hung2019-04-121-1/+1
* | Handle __dummy_o__ and __const[01]__ in read_aiger not abcEddie Hung2019-04-121-0/+4
* | Merge branch 'xaig' of github.com:YosysHQ/yosys into xaigEddie Hung2019-04-121-12/+32
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| * | Fix inout handling for -map optionEddie Hung2019-04-121-10/+30
* | | Also cope with duplicated CIsEddie Hung2019-04-121-5/+23
* | | Cope with an output having same name as an input (i.e. CO)Eddie Hung2019-04-121-5/+23
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* | parse_aiger() to rename all $lut cells after "clean"Eddie Hung2019-04-101-24/+21
* | Fix spacingEddie Hung2019-04-081-29/+29
* | parse_xaiger() to really pass single and multi-bit inout testsEddie Hung2019-02-261-10/+12
* | parse_xaiger() to cope with multi bit inoutsEddie Hung2019-02-261-0/+11
* | parse_xaiger() to untransform $inout.out output portsEddie Hung2019-02-251-5/+20
* | read_aiger to accept empty string for clk_name, passable only if no latchesEddie Hung2019-02-251-0/+2
* | read_aiger to work with symbol tableEddie Hung2019-02-211-8/+47
* | Add attributionEddie Hung2019-02-211-1/+1