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Author
Age
Files
Lines
*
$mem cell in verilog backend : grouped writes by clock
luke whittlesey
2015-06-08
1
-54
/
+108
*
Bug fix in $mem verilog backend + changed tests/bram flow of make test.
luke whittlesey
2015-06-04
1
-14
/
+16
*
Improvements in BLIF front-end
Clifford Wolf
2015-05-24
1
-0
/
+1
*
Some fixes for $mem in verilog back-end
Clifford Wolf
2015-05-20
1
-19
/
+23
*
Merge pull request #63 from wluker/verilog-backend-mem
Clifford Wolf
2015-05-11
1
-1
/
+2
|
\
|
*
Fixed bug in $mem cell verilog code generation.
luke whittlesey
2015-05-11
1
-11
/
+12
*
|
Disabled broken $mem support in verilog backend
Clifford Wolf
2015-05-10
1
-11
/
+11
|
/
*
Made changes recommended by Clifford Wolf ...
luke whittlesey
2015-05-10
1
-22
/
+11
*
Verilog backend for $mem cells should now be able to handle different
luke whittlesey
2015-05-08
1
-50
/
+105
*
Added support for $mem cells in the verilog backend.
luke whittlesey
2015-05-07
1
-1
/
+120
*
Minor fixes in handling of "init" attribute
Clifford Wolf
2015-04-09
1
-7
/
+7
*
Removed "techmap -share_map" (use "-map +/filename" instead)
Clifford Wolf
2015-04-08
1
-1
/
+1
*
Added "port_directions" to write_json output
Clifford Wolf
2015-04-06
1
-0
/
+20
*
Added "init" attribute support to verilog backend
Clifford Wolf
2015-04-04
1
-0
/
+5
*
Update README
Ahmed Irfan
2015-04-03
1
-1
/
+1
*
Delete btor.ys
Ahmed Irfan
2015-04-03
1
-18
/
+0
*
Update README
Ahmed Irfan
2015-04-03
1
-1
/
+1
*
separated memory next from write cell
Ahmed Irfan
2015-04-03
1
-7
/
+55
*
Added Verilog backend $dffsr support
Clifford Wolf
2015-03-18
1
-1
/
+51
*
Documentation for JSON format, added attributes
Clifford Wolf
2015-03-06
1
-16
/
+156
*
Json bugfix
Clifford Wolf
2015-03-03
1
-1
/
+1
*
Json backend improvements
Clifford Wolf
2015-03-03
1
-4
/
+12
*
Added write_blif -attr
Clifford Wolf
2015-03-02
1
-18
/
+33
*
Added JSON backend
Clifford Wolf
2015-03-02
2
-0
/
+262
*
Added $assume support to write_smt2
Clifford Wolf
2015-02-26
1
-4
/
+19
*
Minor "write_smt2" help msg change
Clifford Wolf
2015-02-22
1
-1
/
+1
*
Added "<mod>_a" and "<mod>_i" to write_smt2 output
Clifford Wolf
2015-02-22
1
-23
/
+149
*
Fixed "write_verilog -attr2comment" handling of "*/" in strings
Clifford Wolf
2015-02-13
1
-2
/
+4
*
Added EDIF backend support for multi-bit cell ports
Clifford Wolf
2015-02-01
1
-11
/
+10
*
Shorter "dump" options
Clifford Wolf
2015-01-31
1
-4
/
+4
*
Added ENABLE_NDEBUG makefile options
Clifford Wolf
2015-01-24
2
-2
/
+4
*
Added dict/pool.sort()
Clifford Wolf
2015-01-24
2
-50
/
+26
*
Cosmetic changes in verilog output format
Clifford Wolf
2015-01-02
1
-5
/
+10
*
Fixed memory->start_offset handling
Clifford Wolf
2015-01-01
1
-0
/
+2
*
Replaced std::unordered_map as implementation for Yosys::dict
Clifford Wolf
2014-12-26
2
-42
/
+42
*
Added Yosys::{dict,nodict,vector} container types
Clifford Wolf
2014-12-26
1
-1
/
+1
*
Various fixes and improvements in "write_smt2 -bv"
Clifford Wolf
2014-12-25
3
-11
/
+43
*
Various fixes and improvements in write_smt2
Clifford Wolf
2014-12-25
2
-32
/
+88
*
Added support for most BV cell types to write_smt2
Clifford Wolf
2014-12-25
1
-14
/
+221
*
Added "write_smt2 -bv" and other write_smt2 improvements
Clifford Wolf
2014-12-25
1
-172
/
+153
*
Added write_smt2 (only gate level logic supported so far)
Clifford Wolf
2014-12-24
2
-0
/
+353
*
Renamed extend() to extend_xx(), changed most users to extend_u0()
Clifford Wolf
2014-12-24
1
-1
/
+1
*
Added $dffe support to write_verilog
Clifford Wolf
2014-12-20
1
-3
/
+14
*
Fixed another bug in write_blif handling of $lut cells
Clifford Wolf
2014-12-19
1
-1
/
+1
*
Fixed writing of $lut cells in BLIF backend
Clifford Wolf
2014-12-17
1
-7
/
+7
*
Added "write_blif -undef" and support for special "-" true/false/undef type
Clifford Wolf
2014-12-14
1
-13
/
+33
*
Added "write_blif -blackbox"
Clifford Wolf
2014-12-14
1
-2
/
+16
*
Added "blif -unbuf" feature
Clifford Wolf
2014-12-14
1
-0
/
+19
*
Added log_warning() API
Clifford Wolf
2014-11-09
1
-1
/
+1
*
Fixed generation of temp names in verilog backend
Clifford Wolf
2014-11-07
1
-4
/
+5
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