aboutsummaryrefslogtreecommitdiffstats
path: root/backends
Commit message (Expand)AuthorAgeFilesLines
* Merge pull request #2563 from whitequark/cxxrtl-msvcwhitequark2021-01-262-10/+10
|\
| * cxxrtl: do not use `->template` for non-dependent names.whitequark2021-01-262-10/+10
* | Improves the previous commit with a more complete coverage of the casesIris Johnson2021-01-151-12/+12
* | Handle sliced bits as clock inputs (fixes #2542)Iris Johnson2021-01-141-3/+11
|/
* add buffer option to spice backendPepijn de Vos2021-01-131-7/+15
* cxxrtl: don't crash generating debug information for unused wires.whitequark2020-12-221-9/+10
* cxxrtl: split processes into sync and case nodes.whitequark2020-12-221-11/+26
* cxxrtl: completely rewrite netlist layout code.whitequark2020-12-221-406/+569
* cxxrtl: simplify logic choosing wire type. NFCI.whitequark2020-12-211-19/+8
* cxxrtl: clarify node use-def construction. NFCI.whitequark2020-12-211-18/+11
* cxxrtl: fix typo.whitequark2020-12-211-2/+2
* cxxrtl: speed up bit repeats (sign extends, etc).whitequark2020-12-212-5/+28
* cxxrtl: speed up commits on clang.whitequark2020-12-211-3/+3
* cxxrtl: use `static inline` instead of `inline` in the C API.whitequark2020-12-201-1/+1
* cxxrtl: print names of cells inlined in connections.whitequark2020-12-151-1/+10
* cxxrtl: disable optimization of debug_items().whitequark2020-12-152-3/+15
* cxxrtl: make alias analysis outlining-aware.whitequark2020-12-151-38/+48
* cxxrtl: add a "bare minimum" debug information level.whitequark2020-12-141-9/+17
* cxxrtl: implement debug information outlining.whitequark2020-12-145-71/+278
* cxxrtl: rename "elision" to "inlining". NFC.whitequark2020-12-131-77/+77
* cxxrtl: fix outdated comment. NFC.whitequark2020-12-131-2/+2
* cxxrtl: use IdString::isPublic(). NFC.whitequark2020-12-131-4/+4
* cxxrtl: don't overwrite buffered inputs.whitequark2020-12-112-25/+33
* cxxrtl: allow customizing the root module path in the C API.whitequark2020-12-032-1/+20
* Merge pull request #2468 from whitequark/cxxrtl-assertwhitequark2020-12-022-2/+16
|\
| * cxxrtl: use CXXRTL_ASSERT for RTL contract violations instead of assert.whitequark2020-12-022-2/+16
* | Merge pull request #2469 from whitequark/cxxrtl-no-clkwhitequark2020-12-021-6/+14
|\ \
| * | cxxrtl: fix crashes caused by a floating or constant clock input.whitequark2020-12-021-6/+14
| |/
* / cxxrtl: provide a way to perform unobtrusive power-on reset.whitequark2020-12-024-3/+78
|/
* Add verilog backend option for simple_lhsMiodrag Milanovic2020-11-251-6/+22
* generate only simple assignments in verilog backendMiodrag Milanovic2020-11-251-5/+9
* Merge pull request #2295 from epfl-vlsc/firrtl_blackbox_generic_parametersMiodrag Milanović2020-11-241-58/+294
|\
| * Formatting fixesSahand Kashani2020-11-231-10/+7
| * Add support for real-valued parameters + preserve type of parametersSahand Kashani2020-08-061-38/+113
| * Add firrtl backend support for generic parameters in blackbox componentsSahand Kashani2020-07-231-58/+222
* | backends/blif: Remove unused vector of strings (#2420)William Woodruff2020-11-161-57/+53
* | cxxrtl: run `hierarchy -auto-top` if no top module is present.whitequark2020-11-021-7/+26
* | cxxrtl: don't assert on non-constant $meminit inputs.whitequark2020-11-011-2/+4
* | cxxrtl: don't assert on wires with multiple drivers.whitequark2020-11-011-0/+2
* | btor: Use Mem helper.Marcelina Kościelnicka2020-10-211-93/+102
* | smt2: Use Mem helper.Marcelina Kościelnicka2020-10-211-186/+244
* | verilog_backend: Use Mem helper.Marcelina Kościelnicka2020-10-211-274/+251
* | smtbmc: escape identifiers in verilog testbenchJakob Wenzel2020-10-061-11/+29
* | write_verilog: emit intermediate wire for constant values in sensitivity listN. Engelhardt2020-09-281-7/+53
* | Merge pull request #2372 from nakengelhardt/name_is_publicN. Engelhardt2020-09-214-8/+8
|\ \
| * | use the new isPublic() in a few placesN. Engelhardt2020-09-144-8/+8
* | | Merge pull request #2369 from Xiretza/gitignoresMiodrag Milanović2020-09-102-0/+2
|\ \ \ | |/ / |/| |
| * | Add missing gitignores for test artifactsXiretza2020-08-312-0/+2
* | | cxxrtl: expose driver kind in debug information.whitequark2020-09-023-12/+112
* | | cxxrtl: improve handling of FFs with async inputs (other than CLK).whitequark2020-09-021-22/+23
generated by cgit v1.2.3 (git 2.25.1) at 2025-09-18 07:38:21 +0000
; log(" -retime\n"); log(" run 'abc' with -dff option\n"); log("\n"); log("\n"); log("The following commands are executed by this synthesis command:\n"); log("\n"); log(" begin:\n"); log(" read_verilog -lib +/xilinx/cells_sim.v\n"); log(" read_verilog -lib +/xilinx/cells_xtra.v\n"); log(" read_verilog -lib +/xilinx/brams_bb.v\n"); log(" read_verilog -lib +/xilinx/drams_bb.v\n"); log(" hierarchy -check -top <top>\n"); log("\n"); log(" flatten: (only if -flatten)\n"); log(" proc\n"); log(" flatten\n"); log("\n"); log(" coarse:\n"); log(" synth -run coarse\n"); log("\n"); log(" bram:\n"); log(" memory_bram -rules +/xilinx/brams.txt\n"); log(" techmap -map +/xilinx/brams_map.v\n"); log("\n"); log(" dram:\n"); log(" memory_bram -rules +/xilinx/drams.txt\n"); log(" techmap -map +/xilinx/drams_map.v\n"); log("\n"); log(" fine:\n"); log(" opt -fast -full\n"); log(" memory_map\n"); log(" dffsr2dff\n"); log(" dff2dffe\n"); log(" opt -full\n"); log(" techmap -map +/techmap.v -map +/xilinx/arith_map.v\n"); log(" opt -fast\n"); log("\n"); log(" map_luts:\n"); log(" abc -luts 2:2,3,6:5,10,20 [-dff]\n"); log(" clean\n"); log("\n"); log(" map_cells:\n"); log(" techmap -map +/xilinx/cells_map.v\n"); log(" dffinit -ff FDRE Q INIT -ff FDCE Q INIT -ff FDPE Q INIT\n"); log(" clean\n"); log("\n"); log(" check:\n"); log(" hierarchy -check\n"); log(" stat\n"); log(" check -noinit\n"); log("\n"); log(" edif: (only if -edif)\n"); log(" write_edif <file-name>\n"); log("\n"); } virtual void execute(std::vector<std::string> args, RTLIL::Design *design) { std::string top_opt = "-auto-top"; std::string edif_file; std::string run_from, run_to; bool flatten = false; bool retime = false; size_t argidx; for (argidx = 1; argidx < args.size(); argidx++) { if (args[argidx] == "-top" && argidx+1 < args.size()) { top_opt = "-top " + args[++argidx]; continue; } if (args[argidx] == "-edif" && argidx+1 < args.size()) { edif_file = args[++argidx]; continue; } if (args[argidx] == "-run" && argidx+1 < args.size()) { size_t pos = args[argidx+1].find(':'); if (pos == std::string::npos) break; run_from = args[++argidx].substr(0, pos); run_to = args[argidx].substr(pos+1); continue; } if (args[argidx] == "-flatten") { flatten = true; continue; } if (args[argidx] == "-retime") { retime = true; continue; } break; } extra_args(args, argidx, design); if (!design->full_selection()) log_cmd_error("This comannd only operates on fully selected designs!\n"); bool active = run_from.empty(); log_header(design, "Executing SYNTH_XILINX pass.\n"); log_push(); if (check_label(active, run_from, run_to, "begin")) { Pass::call(design, "read_verilog -lib +/xilinx/cells_sim.v"); Pass::call(design, "read_verilog -lib +/xilinx/cells_xtra.v"); Pass::call(design, "read_verilog -lib +/xilinx/brams_bb.v"); Pass::call(design, "read_verilog -lib +/xilinx/drams_bb.v"); Pass::call(design, stringf("hierarchy -check %s", top_opt.c_str())); } if (flatten && check_label(active, run_from, run_to, "flatten")) { Pass::call(design, "proc"); Pass::call(design, "flatten"); } if (check_label(active, run_from, run_to, "coarse")) { Pass::call(design, "synth -run coarse"); } if (check_label(active, run_from, run_to, "bram")) { Pass::call(design, "memory_bram -rules +/xilinx/brams.txt"); Pass::call(design, "techmap -map +/xilinx/brams_map.v"); } if (check_label(active, run_from, run_to, "dram")) { Pass::call(design, "memory_bram -rules +/xilinx/drams.txt"); Pass::call(design, "techmap -map +/xilinx/drams_map.v"); } if (check_label(active, run_from, run_to, "fine")) { Pass::call(design, "opt -fast -full"); Pass::call(design, "memory_map"); Pass::call(design, "dffsr2dff"); Pass::call(design, "dff2dffe"); Pass::call(design, "opt -full"); Pass::call(design, "techmap -map +/techmap.v -map +/xilinx/arith_map.v"); Pass::call(design, "opt -fast"); } if (check_label(active, run_from, run_to, "map_luts")) { Pass::call(design, "abc -luts 2:2,3,6:5,10,20" + string(retime ? " -dff" : "")); Pass::call(design, "clean"); } if (check_label(active, run_from, run_to, "map_cells")) { Pass::call(design, "techmap -map +/xilinx/cells_map.v"); Pass::call(design, "dffinit -ff FDRE Q INIT -ff FDCE Q INIT -ff FDPE Q INIT"); Pass::call(design, "clean"); } if (check_label(active, run_from, run_to, "check")) { Pass::call(design, "hierarchy -check"); Pass::call(design, "stat"); Pass::call(design, "check -noinit"); } if (check_label(active, run_from, run_to, "edif")) { if (!edif_file.empty()) Pass::call(design, stringf("write_edif %s", edif_file.c_str())); } log_pop(); } } SynthXilinxPass; PRIVATE_NAMESPACE_END
generated by cgit v1.2.3 (git 2.25.1) at 2025-09-18 07:38:21 +0000