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* | cxxrtl: add missing namespace.whitequark2020-06-091-2/+2
|/ | | | Fixes #2124.
* cxxrtl: fix format of hdlnames.whitequark2020-06-081-1/+1
| | | | | The CXXRTL code that handled the `hdlname` attribute implemented outdated semantics.
* cxxrtl: don't check immutable values for changes in VCD writer.whitequark2020-06-081-4/+10
| | | | | | | | | | | This commit changes the VCD writer such that for all signals that have `debug_item.type == VALUE && debug_item.next == nullptr`, it would only sample the value once. Commit f2d7a187 added more debug information by including constant wires, and decreased the performance of VCD writer proportionally because the constant wires were still repeatedly sampled; this commit eliminates the performance hit.
* cxxrtl: emit debug information for constant wires.whitequark2020-06-083-17/+44
| | | | | | | | | Constant wires can represent a significant chunk of the design in generic designs or after optimization. Emitting them in VCD files significantly improves usability because gtkwave removes all traces that are not present in the VCD file after reload, and iterative development suffers if switching a varying signal to a constant disrupts the workflow.
* cxxrtl: track aliases in VCD writer.whitequark2020-06-081-10/+14
| | | | | | | | | | | This commit changes the VCD writer such that for all signals that share `debug_item.curr`, it would only emit a single VCD identifier, and sample the value once. Commit 9b39c6f7 added redundancy to debug information by including alias wires, and increased the size of VCD files proportionally; this commit eliminates the redundancy from VCD files so that their size is the same as before.
* cxxrtl: emit debug information for alias wires.whitequark2020-06-081-3/+55
| | | | | | | Alias wires can represent a significant chunk of the design in highly hierarchical designs; in Minerva SRAM, there are 273 member wires and 527 alias wires. Showing them in every hierarchy level significantly improves usability.
* cxxrtl: fix typo in comment. NFC.whitequark2020-06-081-4/+4
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* cxxrtl: minor debug-related improvements.whitequark2020-06-081-2/+3
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* cxxrtl: rename cxxrtl.cc→cxxrtl_backend.cc.whitequark2020-06-072-1/+1
| | | | | To avoid confusion with the C++ source files that are a part of the simulation itself and not a part of Yosys build.
* cxxrtl: add a C API for writing VCD dumps.whitequark2020-06-075-2/+204
| | | | This C API is fully featured.
* cxxrtl: only write VCD values that were actually updated.whitequark2020-06-071-10/+30
| | | | | On a representative design (Minerva SoC) this reduces VCD file size by ~20× and runtime by ~3×.
* cxxrtl: add a VCD writer using debug information.whitequark2020-06-071-0/+194
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* cxxrtl: add a C API for driving and introspecting designs.whitequark2020-06-064-29/+291
| | | | | | Compared to the C++ API, the C API currently has two limitations: 1. Memories cannot be updated in a race-free way. 2. Black boxes cannot be implemented in C.
* cxxrtl: generate debug information for non-localized public wires.whitequark2020-06-062-2/+131
| | | | | | | | | | Debug information describes values, wires, and memories with a simple C-compatible layout. It can be emitted on demand into a map, which has no runtime cost when it is unused, and allows late bound designs. The `hdlname` attribute is used as the lookup key such that original names, as emitted by the frontend, can be used for debugging and introspection.
* Merge pull request #2110 from BracketMaster/masterwhitequark2020-06-061-1/+1
|\ | | | | MacOS has even stricter stack limits in catalina.
| * more reasonable numbers for memoryYehowshua Immanuel2020-06-041-1/+1
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| * MacOS has even stricter stack limits in catalina.Yehowshua Immanuel2020-06-041-1/+1
| | | | | | Invoking sby in macOS Catalina fails because of bizarre stack limits in Catalina.
* | Merge pull request #2113 from whitequark/cxxrtl-fix-sshrwhitequark2020-06-051-1/+1
|\ \ | | | | | | cxxrtl: fix implementation of $sshr cell
| * | cxxrtl: fix implementation of $sshr cell.whitequark2020-06-051-1/+1
| | | | | | | | | | | | Fixes #2111.
* | | Merge pull request #2109 from nakengelhardt/btor_internal_namesN. Engelhardt2020-06-051-5/+5
|\ \ \ | |_|/ |/| | btor backend: make not printing internal names default
| * | btor backend: make not printing internal names defaultN. Engelhardt2020-06-041-5/+5
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* | | Merge pull request #2077 from YosysHQ/eddie/abc9_dff_improveEddie Hung2020-06-041-28/+22
|\ \ \ | |/ / |/| | abc9: -dff improvements
| * | xaiger: cleanupEddie Hung2020-05-251-28/+22
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* | | Add printf format attributes to btorf/infof helper functionsClaire Wolf2020-06-041-3/+3
| | | | | | | | | | | | Signed-off-by: Claire Wolf <claire@symbioticeda.com>
* | | btor backend: add option to not include internal namesN. Engelhardt2020-06-041-33/+42
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* | | Merge pull request #2006 from jersey99/signed-in-rtlil-wirewhitequark2020-06-042-0/+6
|\ \ \ | | | | | | | | Preserve 'signed'-ness of a verilog wire through RTLIL
| * | | Preserve 'signed'-ness of a verilog wire through RTLILVamsi K Vytla2020-04-272-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | As per suggestion made in https://github.com/YosysHQ/yosys/pull/1987, now: RTLIL::wire holds an is_signed field. This is exported in JSON backend This is exported via dump_rtlil command This is read in via ilang_parser
* | | | Merge pull request #2082 from YosysHQ/eddie/abc9_scc_fixesEddie Hung2020-06-031-1/+1
|\ \ \ \ | |_|_|/ |/| | | abc9: fixes around handling combinatorial loops
| * | | xaiger: promote abc9_keep wiresEddie Hung2020-05-251-1/+1
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* | | Merge pull request #2018 from boqwxp/qbfsat-timeoutclairexen2020-05-302-5/+31
|\ \ \ | | | | | | | | smtbmc and qbfsat: Add timeout option to set solver timeouts for Z3, Yices, and CVC4.
| * | | smtbmc: Remove superfluous `yosys-smt2-timeout` file macro.Alberto Gonzalez2020-05-291-4/+0
| | | | | | | | | | | | | | | | Co-Authored-By: clairexen <claire@symbioticeda.com>
| * | | smtbmc and qbfsat: Add timeout option to set solver timeouts for Z3, Yices, ↵Alberto Gonzalez2020-05-252-5/+35
| | | | | | | | | | | | | | | | and CVC4.
* | | | Merge pull request #1885 from Xiretza/mod-rem-cellsclairexen2020-05-297-9/+116
|\ \ \ \ | | | | | | | | | | Fix modulo/remainder semantics
| * | | | Add flooring division operatorXiretza2020-05-283-3/+58
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The $div and $mod cells use truncating division semantics (rounding towards 0), as defined by e.g. Verilog. Another rounding mode, flooring (rounding towards negative infinity), can be used in e.g. VHDL. The new $divfloor cell provides this flooring division. This commit also fixes the handling of $div in opt_expr, which was previously optimized as if it was $divfloor.
| * | | | Add flooring modulo operatorXiretza2020-05-287-9/+61
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The $div and $mod cells use truncating division semantics (rounding towards 0), as defined by e.g. Verilog. Another rounding mode, flooring (rounding towards negative infinity), can be used in e.g. VHDL. The new $modfloor cell provides this flooring modulo (also known as "remainder" in several languages, but this name is ambiguous). This commit also fixes the handling of $mod in opt_expr, which was previously optimized as if it was $modfloor.
* | | | | Merge pull request #2016 from boqwxp/qbfsat-yicesclairexen2020-05-291-1/+5
|\ \ \ \ \ | |/ / / / |/| / / / | |/ / / qbfsat: Add `-solver` option and allow choice of Z3 or Yices, making Yices the default.
| * | | qbfsat: Move SMT2 info statements back to the top of the file.Alberto Gonzalez2020-05-251-3/+3
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| * | | qbfsat: Add `-solver` option and allow choice of Z3 or Yices, making Yices ↵Alberto Gonzalez2020-05-251-3/+7
| |/ / | | | | | | | | | | | | | | | the default. Ensures that "BV" is the logic whenever solving an exists-forall problem with Yices, moves the "(set-logic ...)" directive above any non-info line, sets the `ef-max-iters` parameter to a very high number when using Yices in exists-forall mode so as not to prematurely abandon difficult problems, and does not provide the incompatible "--incremental" Yices argument when in exists-forall mode.
* | | Merge pull request #2031 from epfl-vlsc/masterwhitequark2020-05-281-1/+40
|\ \ \ | | | | | | | | Add extmodule support to firrtl backend
| * | | Formatting fixesSahand Kashani2020-05-061-14/+7
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| * | | Add extmodule support to firrtl backendSahand Kashani2020-05-061-1/+47
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The current firrtl backend emits blackboxes as standard modules with an empty body, but this causes the firrtl compiler to optimize out entire circuits due to the absence of any drivers. Yosys already tags blackboxes with a (*blackbox*) attribute, so this commit just propagates this change to firrtl's syntax for blackboxes.
* | | | Merge pull request #2063 from boqwxp/techmapped-firrtlwhitequark2020-05-281-10/+12
|\ \ \ \ | | | | | | | | | | firrtl: Accept techmapped cell types in FIRRTL backend.
| * | | | firrtl: Accept techmapped cell types in FIRRTL backend.Alberto Gonzalez2020-05-171-10/+12
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* | | | | cxxrtl: make logging a little bit nicer.whitequark2020-05-261-2/+10
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* | | | | cxxrtl: add missing parts of commit 281c9685.whitequark2020-05-261-5/+3
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* | | | xaiger: do not derive cellsEddie Hung2020-05-241-7/+1
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* | | | cxxrtl: get rid of -O5 aka `opt_clean -purge` optimization level.whitequark2020-05-221-8/+2
| | | | | | | | | | | | | | | | | | | | | | | | This isn't actually necessary anymore after scheduling was improved, and `clean -purge` disrupts the mapping between wires in the input RTLIL netlist and the output CXXRTL code.
* | | | Merge pull request #2054 from boqwxp/fix-smtbmcN. Engelhardt2020-05-201-3/+3
|\ \ \ \ | | | | | | | | | | smtbmc: Fix return status handling.
| * | | | smtbmc: Fix typo in error message.Alberto Gonzalez2020-05-191-1/+1
| | | | | | | | | | | | | | | | | | | | Co-Authored-By: N. Engelhardt <nak@symbioticeda.com>
| * | | | smtbmc: Fix return status handling.Alberto Gonzalez2020-05-141-2/+2
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