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* Import more std:: stuff into Yosys namespaceClifford Wolf2015-10-252-7/+7
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* renamed SigSpec::to_single_sigbit() to SigSpec::as_bit(), added is_bit()Clifford Wolf2015-10-241-2/+2
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* Progress in yosys-smtbmcClifford Wolf2015-10-151-4/+10
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* Improvements in yosys-smtbmcClifford Wolf2015-10-153-2/+9
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* More "yosys-smtbmc -c" fixesClifford Wolf2015-10-142-9/+30
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* Fixed yosys-smtbmc -cClifford Wolf2015-10-141-2/+2
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* Added yosys-smtbmc copyrightClifford Wolf2015-10-143-1/+36
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* Improvements in yosys-smtbmcClifford Wolf2015-10-143-21/+38
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* Added yosys-smtbmcClifford Wolf2015-10-142-1/+20
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* Implemented smtbmc.py -iClifford Wolf2015-10-141-25/+60
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* Added smtbmc.pyClifford Wolf2015-10-134-0/+409
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* Added write_smt2 -wiresClifford Wolf2015-10-131-7/+15
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* Bugfixes in writing of memories as VerilogClifford Wolf2015-09-251-7/+8
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* Added "yosys-smt2-wire" tag support to smt2 back-endClifford Wolf2015-08-311-0/+2
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* Fixed generation of smt2 concat statementsClifford Wolf2015-08-151-3/+5
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* Another block of spelling fixesLarry Doolittle2015-08-143-4/+4
| | | | Smaller this time
* Re-created command-reference-manual.tex, copied some doc fixes to online helpClifford Wolf2015-08-141-3/+3
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* Spell check (by Larry Doolittle)Clifford Wolf2015-08-142-3/+3
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* Added "write_smt2 -regs"Clifford Wolf2015-08-121-7/+36
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* Added SMV back-end 'test_cells.sh' scriptClifford Wolf2015-08-121-0/+33
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* Use MEMID as name for $mem cellClifford Wolf2015-08-091-1/+6
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* Remove some very strange whitespace in btor.cc (by Larry Doolittle)Clifford Wolf2015-08-051-7/+7
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* Bugfix in SMV back-end for partially unassigned wiresClifford Wolf2015-08-051-4/+16
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* Added $assert support to SMV back-endClifford Wolf2015-08-041-4/+21
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* Improvements in BLIF back-endClifford Wolf2015-07-291-5/+84
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* Fixed trailing whitespacesClifford Wolf2015-07-0213-114/+114
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* Added init support to SMV back-endClifford Wolf2015-06-191-1/+3
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* Progress in SMV back-endClifford Wolf2015-06-191-64/+115
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* Progress in SMV back-endClifford Wolf2015-06-191-13/+59
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* Progress in SMV back-endClifford Wolf2015-06-181-24/+94
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* Progress in SMV back-endClifford Wolf2015-06-171-11/+72
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* Progress in SMV back-endClifford Wolf2015-06-171-11/+64
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* Progress in SMV back-endClifford Wolf2015-06-161-3/+46
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* Progress in SMV back-endClifford Wolf2015-06-151-2/+95
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* Progress in SMV back-endClifford Wolf2015-06-151-7/+85
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* Added "write_smv" skeletonClifford Wolf2015-06-152-0/+261
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* Removed debug code from write_smt2Clifford Wolf2015-06-141-2/+0
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* Added write_smt2 -memClifford Wolf2015-06-141-80/+157
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* Fixed cstr_buf for std::string with small string optimizationClifford Wolf2015-06-112-2/+2
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* Improvements in cellaigs.cc and "json -aig"Clifford Wolf2015-06-111-6/+63
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* AigMaker refactoringClifford Wolf2015-06-101-1/+1
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* Added "json -aig"Clifford Wolf2015-06-101-9/+63
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* $mem cell in verilog backend : grouped writes by clockluke whittlesey2015-06-081-54/+108
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* Bug fix in $mem verilog backend + changed tests/bram flow of make test.luke whittlesey2015-06-041-14/+16
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* Improvements in BLIF front-endClifford Wolf2015-05-241-0/+1
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* Some fixes for $mem in verilog back-endClifford Wolf2015-05-201-19/+23
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* Merge pull request #63 from wluker/verilog-backend-memClifford Wolf2015-05-111-1/+2
|\ | | | | Fixed bug in $mem cell verilog code generation.
| * Fixed bug in $mem cell verilog code generation.luke whittlesey2015-05-111-11/+12
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* | Disabled broken $mem support in verilog backendClifford Wolf2015-05-101-11/+11
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* Made changes recommended by Clifford Wolf ...luke whittlesey2015-05-101-22/+11
| | | | | | Removed bit_check_equal(), used RTLIL::SigBit for individual bits, used dict<> instead of std::map, and used RTLIL::SigSpec instead of std::vector.
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