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backends
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verilog
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verilog_backend.cc
Commit message (
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Author
Age
Files
Lines
*
$mem cell in verilog backend : grouped writes by clock
luke whittlesey
2015-06-08
1
-54
/
+108
*
Bug fix in $mem verilog backend + changed tests/bram flow of make test.
luke whittlesey
2015-06-04
1
-14
/
+16
*
Some fixes for $mem in verilog back-end
Clifford Wolf
2015-05-20
1
-19
/
+23
*
Merge pull request #63 from wluker/verilog-backend-mem
Clifford Wolf
2015-05-11
1
-1
/
+2
|
\
|
*
Fixed bug in $mem cell verilog code generation.
luke whittlesey
2015-05-11
1
-11
/
+12
*
|
Disabled broken $mem support in verilog backend
Clifford Wolf
2015-05-10
1
-11
/
+11
|
/
*
Made changes recommended by Clifford Wolf ...
luke whittlesey
2015-05-10
1
-22
/
+11
*
Verilog backend for $mem cells should now be able to handle different
luke whittlesey
2015-05-08
1
-50
/
+105
*
Added support for $mem cells in the verilog backend.
luke whittlesey
2015-05-07
1
-1
/
+120
*
Minor fixes in handling of "init" attribute
Clifford Wolf
2015-04-09
1
-7
/
+7
*
Added "init" attribute support to verilog backend
Clifford Wolf
2015-04-04
1
-0
/
+5
*
Added Verilog backend $dffsr support
Clifford Wolf
2015-03-18
1
-1
/
+51
*
Fixed "write_verilog -attr2comment" handling of "*/" in strings
Clifford Wolf
2015-02-13
1
-2
/
+4
*
Added dict/pool.sort()
Clifford Wolf
2015-01-24
1
-0
/
+2
*
Cosmetic changes in verilog output format
Clifford Wolf
2015-01-02
1
-5
/
+10
*
Replaced std::unordered_map as implementation for Yosys::dict
Clifford Wolf
2014-12-26
1
-25
/
+25
*
Added Yosys::{dict,nodict,vector} container types
Clifford Wolf
2014-12-26
1
-1
/
+1
*
Added $dffe support to write_verilog
Clifford Wolf
2014-12-20
1
-3
/
+14
*
Fixed generation of temp names in verilog backend
Clifford Wolf
2014-11-07
1
-4
/
+5
*
Renamed SIZE() to GetSize() because of name collision on Win32
Clifford Wolf
2014-10-10
1
-1
/
+1
*
namespace Yosys
Clifford Wolf
2014-09-27
1
-4
/
+3
*
Various bug fixes (related to $macc model testing)
Clifford Wolf
2014-09-06
1
-1
/
+2
*
Removed $bu0 cell type
Clifford Wolf
2014-09-04
1
-1
/
+0
*
Using $pos models for $bu0
Clifford Wolf
2014-09-03
1
-16
/
+1
*
Changed backend-api from FILE to std::ostream
Clifford Wolf
2014-08-23
1
-230
/
+230
*
Fixed AOI/OAI expr handling in verilog backend
Clifford Wolf
2014-08-16
1
-4
/
+4
*
Added additional gate types: $_NAND_ $_NOR_ $_XNOR_ $_AOI3_ $_OAI3_ $_AOI4_ $...
Clifford Wolf
2014-08-16
1
-4
/
+40
*
Renamed $_INV_ cell type to $_NOT_
Clifford Wolf
2014-08-15
1
-1
/
+1
*
Refactoring of CellType class
Clifford Wolf
2014-08-14
1
-10
/
+28
*
Be more conservative with printing decimal numbers in verilog backend
Clifford Wolf
2014-08-02
1
-2
/
+3
*
Improved verilog output for ordinary $mux cells
Clifford Wolf
2014-08-02
1
-3
/
+19
*
More cleanups related to RTLIL::IdString usage
Clifford Wolf
2014-08-02
1
-6
/
+6
*
Renamed port access function on RTLIL::Cell, added param access functions
Clifford Wolf
2014-07-31
1
-40
/
+40
*
Added support for "upto" wires to Verilog front- and back-end
Clifford Wolf
2014-07-28
1
-9
/
+22
*
Using log_assert() instead of assert()
Clifford Wolf
2014-07-28
1
-3
/
+2
*
Refactoring: Renamed RTLIL::Design::modules to modules_
Clifford Wolf
2014-07-27
1
-1
/
+1
*
Refactoring: Renamed RTLIL::Module::cells to cells_
Clifford Wolf
2014-07-27
1
-3
/
+3
*
Refactoring: Renamed RTLIL::Module::wires to wires_
Clifford Wolf
2014-07-27
1
-4
/
+4
*
Added RTLIL::Cell::has(portname)
Clifford Wolf
2014-07-26
1
-2
/
+2
*
Manual fixes for new cell connections API
Clifford Wolf
2014-07-26
1
-4
/
+4
*
Changed users of cell->connections_ to the new API (sed command)
Clifford Wolf
2014-07-26
1
-43
/
+43
*
Renamed RTLIL::{Module,Cell}::connections to connections_
Clifford Wolf
2014-07-26
1
-43
/
+43
*
Various RTLIL::SigSpec related code cleanups
Clifford Wolf
2014-07-25
1
-21
/
+29
*
Removed RTLIL::SigSpec::optimize()
Clifford Wolf
2014-07-23
1
-3
/
+0
*
SigSpec refactoring: change RTLIL::SigSpec::chunks() to be read-only, created...
Clifford Wolf
2014-07-22
1
-2
/
+2
*
SigSpec refactoring: using the accessor functions everywhere
Clifford Wolf
2014-07-22
1
-29
/
+29
*
SigSpec refactoring: renamed chunks and width to __chunks and __width
Clifford Wolf
2014-07-22
1
-29
/
+29
*
Use functions instead of always blocks for $mux/$pmux/$safe_pmux in verilog b...
Clifford Wolf
2014-07-20
1
-17
/
+21
*
Added support for $bu0 to verilog backend
Clifford Wolf
2014-07-20
1
-0
/
+16
*
Added $slice and $concat cell types
Clifford Wolf
2014-02-07
1
-0
/
+22
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