| Commit message (Expand) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | rtlil: Dump empty connections when whole module is selected. | Marcelina Kościelnicka | 2021-12-12 | 1 | -2/+2 |
| * | Add optimization to rtlil back-end for all-x parameter values | Claire Xenia Wolf | 2021-09-27 | 1 | -9/+13 |
| * | Fixing old e-mail addresses and deadnames | Claire Xenia Wolf | 2021-06-08 | 2 | -2/+2 |
| * | rtlil: Fix process memwr roundtrip. | Marcelina Kościelnicka | 2021-03-23 | 1 | -1/+1 |
| * | Add support for memory writes in processes. | Marcelina Kościelnicka | 2021-03-08 | 1 | -3/+20 |
| * | Replace "ILANG" with "RTLIL" everywhere. | whitequark | 2020-08-26 | 3 | -0/+590 |
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index : iCE40/yosys | |
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