iCE40/yosys - [no description]

	Commit message (Expand)	Author	Age	Files	Lines
*	Refine memory support to deal with general Verilog memory definitions.	Jim Lawson	2019-04-01	1	-30/+173
*	Ensure fid() calls make_id() for consistency; tests/simple/dff_init.v fails	Jim Lawson	2019-03-04	1	-2/+1
*	Fix FIRRTL to Verilog process instance subfield assignment.	Jim Lawson	2019-02-25	1	-8/+20
*	Removed unused variables, functions.	Jim Lawson	2019-02-15	1	-20/+0
*	Update cells supported for verilog to FIRRTL conversion.	Jim Lawson	2019-02-15	1	-48/+225
*	added prefix to FDirection constants, fixing windows build	Miodrag Milanovic	2018-09-21	1	-11/+11
*	Remove unused functions.	Jim Lawson	2018-08-27	1	-10/+0
*	Add support for module instances.	Jim Lawson	2018-08-23	1	-17/+122
*	Consistent use of 'override' for virtual methods in derived classes.	Henner Zeller	2018-07-20	1	-2/+2
*	More progress on Firrtl backend.	Adam Izraelevitz	2017-02-13	3	-27/+181
*	Bugfix: include assign to write-mask	Adam Izraelevitz	2016-11-18	1	-0/+1
*	More progress in FIRRTL back-end	Clifford Wolf	2016-11-18	3	-4/+121
*	Progress in FIRRTL back-end	Clifford Wolf	2016-11-18	4	-5/+55
*	Added first draft of FIRRTL back-end	Clifford Wolf	2016-11-17	2	-0/+353