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* Fixing old e-mail addresses and deadnamesClaire Xenia Wolf2021-06-081-1/+1
| | | | | | | | s/((Claire|Xen|Xenia|Clifford)\s+)+(Wolf|Xen)\s+<(claire|clifford)@(symbioticeda.com|clifford.at|yosyshq.com)>/Claire Xenia Wolf <claire@yosyshq.com>/gi; s/((Nina|Nak|N\.)\s+)+Engelhardt\s+<nak@(symbioticeda.com|yosyshq.com)>/N. Engelhardt <nak@yosyshq.com>/gi; s/((David)\s+)+Shah\s+<(dave|david)@(symbioticeda.com|yosyshq.com|ds0.me)>/David Shah <dave@ds0.me>/gi; s/((Miodrag)\s+)+Milanovic\s+<(miodrag|micko)@(symbioticeda.com|yosyshq.com)>/Miodrag Milanovic <micko@yosyshq.com>/gi; s,https?://www.clifford.at/yosys/,http://yosyshq.net/yosys/,g;
* Make a few passes auto-call Mem::narrow instead of rejecting wide ports.Marcelina Kościelnicka2021-05-281-4/+2
| | | | | | This essentially adds wide port support for free in passes that don't have a usefully better way of handling wide ports than just breaking them up to narrow ports, avoiding "please run memory_narrow" annoyance.
* Reject wide ports in some passes that will never support them.Marcelina Kościelnicka2021-05-251-0/+4
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* backend/firrtl: Convert to use Mem helpers.Marcelina Kościelnicka2021-05-241-264/+88
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* Formatting fixesSahand Kashani2020-11-231-10/+7
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* Add support for real-valued parameters + preserve type of parametersSahand Kashani2020-08-061-38/+113
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This commit adds support for real-valued parameters in blackboxes. Additionally, parameters now retain their types are no longer all encoded as strings. There is a caveat with this implementation due to my limited knowledge of yosys, more specifically to how yosys encodes bitwidths of parameter values. The example below can motivate the implementation choice I took. Suppose a verilog component is declared with the following parameters: parameter signed [26:0] test_signed; parameter [26:0] test_unsigned; parameter signed [40:0] test_signed_large; If you instantiate it as follows: defparam <inst_name> .test_signed = 49; defparam <inst_name> .test_unsigned = 40'd35; defparam <inst_name> .test_signed_large = 40'd12; If you peek in the RTLIL::Const structure corresponding to these params, you realize that parameter "test_signed" is being considered as a 32-bit value since it's declared as "49" without a width specifier, even though the parameter is defined to have a maximum width of 27 bits. A similar issue occurs for parameter "test_unsigned" where it is supposed to take a maximum bit width of 27 bits, but if the user supplies a 40-bit value as above, then yosys considers the value to be 40 bits. I suppose this is due to the type being defined by the RHS rather than the definition. Regardless of this, I emit the same widths as what the user specifies on the RHS when generating firrtl IR.
* Add firrtl backend support for generic parameters in blackbox componentsSahand Kashani2020-07-231-58/+222
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Previous blackbox components were just emitted with their interface ports, but their generic parameters were never emitted and it was therefore impossible to customize them. This commit adds support for blackbox generic parameters, though support is only provided for INTEGER and STRING parameters. Other types of parameters such as DOUBLEs, ..., would result in undefined behavior here. This allows the emission of custom extmodule instances such as the following: extmodule fourteennm_lcell_comb_<instName>: input cin: UInt<1> output combout: UInt<1> output cout: UInt<1> input dataa: UInt<1> input datab: UInt<1> input datac: UInt<1> input datad: UInt<1> input datae: UInt<1> input dataf: UInt<1> input datag: UInt<1> input datah: UInt<1> input sharein: UInt<1> output shareout: UInt<1> output sumout: UInt<1> defname = fourteennm_lcell_comb parameter extended_lut = "off" parameter lut_mask = "b0001001000010010000100100001001000010010000100100001001000010010" parameter shared_arith = "off"
* Use C++11 final/override keywords.whitequark2020-06-181-2/+2
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* Add flooring modulo operatorXiretza2020-05-281-0/+1
| | | | | | | | | | | The $div and $mod cells use truncating division semantics (rounding towards 0), as defined by e.g. Verilog. Another rounding mode, flooring (rounding towards negative infinity), can be used in e.g. VHDL. The new $modfloor cell provides this flooring modulo (also known as "remainder" in several languages, but this name is ambiguous). This commit also fixes the handling of $mod in opt_expr, which was previously optimized as if it was $modfloor.
* Merge pull request #2031 from epfl-vlsc/masterwhitequark2020-05-281-1/+40
|\ | | | | Add extmodule support to firrtl backend
| * Formatting fixesSahand Kashani2020-05-061-14/+7
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| * Add extmodule support to firrtl backendSahand Kashani2020-05-061-1/+47
| | | | | | | | | | | | | | | | | | The current firrtl backend emits blackboxes as standard modules with an empty body, but this causes the firrtl compiler to optimize out entire circuits due to the absence of any drivers. Yosys already tags blackboxes with a (*blackbox*) attribute, so this commit just propagates this change to firrtl's syntax for blackboxes.
* | firrtl: Accept techmapped cell types in FIRRTL backend.Alberto Gonzalez2020-05-171-10/+12
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* | Add YS_FALLTHROUGH macro to mark case fall-throughXiretza2020-05-071-2/+2
|/ | | | | C++17 introduced [[fallthrough]], GCC and clang had their own vendored attributes before that. MSVC doesn't seem to have such a warning at all.
* ast, rpc: record original name of $paramod\* as \hdlname attribute.whitequark2020-04-181-11/+2
| | | | | | | | | | The $paramod name mangling is not invertible (the \ character, which separates the module name from the parameters, is valid in the module name itself), which does not stop people from trying to invert it. This commit makes it easy to invert the name mangling by storing the original name explicitly, and fixes the firrtl backend to use the newly introduced attribute.
* Fix indentationSahand Kashani2020-04-091-3/+3
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* Remove dependency on ilang backend since we no longer use itSahand Kashani2020-04-081-1/+0
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* Merge branch 'master' of github.com:YosysHQ/yosys into firrtl_backend_fileinfoSahand Kashani2020-04-081-112/+112
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| * kernel: big fat patch to use more ID::*, otherwise ID(*)Eddie Hung2020-04-021-88/+88
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| * kernel: use more ID::*Eddie Hung2020-04-021-23/+23
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* | Remove unnecessary pruning of double-quotingSahand Kashani2020-04-081-5/+0
| | | | | | | | | | | | | | | | | | | | | | | | In the past I was calling the ILANG_BACKEND::dump_const() to dump values to an output stream. When these values were strings, the function used to add quotes around them. The firrtl compiler, in turn, escaped these quotes and the result was double-quoted strings which were hard to read. However I'm now calling design_entity->get_src_attribute() directly and there is no additional quote being put around it, so we can safely remove the unnecessary call to str.erase() here.
* | Remove use of auto for simple types + simplify src attribute computationSahand Kashani2020-03-241-10/+5
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* | Refactor to directly call ILANG_BACKEND::dump_const() + directly lookup src ↵Sahand Kashani2020-03-241-68/+15
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* | Indentation conventionsSahand Kashani2020-03-231-5/+6
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* | Const parameter in function (backends/firrtl/firrtl.cc)Sahand Kashani-Akhavan2020-03-231-1/+1
| | | | | | Co-Authored-By: Alberto Gonzalez <61295559+boqwxp@users.noreply.github.com>
* | Strip quotes around fileinfo stringsSahand Kashani2020-03-211-1/+5
| | | | | | | | | | | | Yosys puts quotes around the string that represents the fileinfo whereas firrtl does not. So when firrtl sees quotes, it escapes them with an extra backslash which makes it hard to read afterwards.
* | Add fileinfo to firrtl backend for assignments and non-instance cellsSahand Kashani2020-03-211-21/+30
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* | Refactor fileinfo emission characters to single locationSahand Kashani2020-03-201-6/+8
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* | Add fileinfo to firrtl backend for instancesSahand Kashani2020-03-191-2/+3
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* | Add fileinfo to firrtl backend for modules and wiresSahand Kashani2020-03-191-12/+20
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* | Add fileinfo to firrtl backend for top-level circuitSahand Kashani2020-03-191-1/+62
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* remove include where not usedMiodrag Milanovic2020-03-131-1/+0
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* Merge pull request #1258 from YosysHQ/eddie/cleanupClifford Wolf2019-08-101-5/+5
|\ | | | | Cleanup a few barnacles across codebase
| * substr() -> compare()Eddie Hung2019-08-071-1/+1
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| * Merge remote-tracking branch 'origin/master' into eddie/cleanupEddie Hung2019-08-071-93/+203
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| * | Use IdString::begins_with()Eddie Hung2019-08-061-2/+2
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| * | Use State::S{0,1}Eddie Hung2019-08-061-2/+2
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* | | Merge branch 'master' into firrtl_err_on_unsupported_cellJim Lawson2019-08-071-93/+203
|\ \ \ | | |/ | |/| | | | | | | # Conflicts: # backends/firrtl/firrtl.cc
| * | Support explicit FIRRTL properties for better accommodation of ↵Jim Lawson2019-07-311-93/+203
| |/ | | | | | | | | | | | | | | | | FIRRTL/Verilog semantic differences. Use FIRRTL spec vlaues for definition of FIRRTL widths. Added support for '$pos`, `$pow` and `$xnor` cells. Enable tests/simple/operators.v since all operators tested there are now supported. Disable FIRRTL tests of tests/simple/{defvalue.sv,implicit_ports.v,wandwor.v} since they currently generate FIRRTL compilation errors.
* / Call log_error() instead of log_warning() on unsupported cell type in FIRRTL ↵Jim Lawson2019-07-241-1/+1
|/ | | | backend.
* Fix static shift operands, neg result type, minor formattingJim Lawson2019-05-211-3/+7
| | | | | | Static shift operands must be constants. The result of FIRRTL's neg operator is signed. Fix poor indentation for gen_read().
* Fix all warnings that occurred when compiling with gcc9Kristoffer Ellersgaard Koch2019-05-081-1/+2
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* Re-indent firrtl.cc:struct memory - no functional change.Jim Lawson2019-05-011-25/+25
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* Fix #938 - Crash occurs in case when use write_firrtl commandJim Lawson2019-05-011-4/+41
| | | | | | Add missing memory initialization. Sanity-check memory parameters. Add Cell pointer to memory object (for error reporting).
* Refine memory support to deal with general Verilog memory definitions.Jim Lawson2019-04-011-30/+173
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* Ensure fid() calls make_id() for consistency; tests/simple/dff_init.v failsJim Lawson2019-03-041-2/+1
| | | | Mark dff_init.v as expected to fail since it uses "initial value".
* Fix FIRRTL to Verilog process instance subfield assignment.Jim Lawson2019-02-251-8/+20
| | | | | | Don't emit subfield assignments: bits(x, y, z) <= ... - but instead, add them to the reverse-wire-map where they'll be treated at the end of the module. Enable tests which were disabled due to incorrect treatment of subfields. Assume the `$firrtl2verilog` variable contains any additional switches to control verilog generation (i.e. `--no-dedup -X mverilog`)
* Removed unused variables, functions.Jim Lawson2019-02-151-20/+0
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* Update cells supported for verilog to FIRRTL conversion.Jim Lawson2019-02-151-48/+225
| | | | | | | | | | | | | Issue warning messages for missing parameterized modules and attempts to set initial values. Replace simple "if (cell-type)" with "else if" chain. Fix FIRRTL shift handling. Add support for parameterized modules, $shift, $shiftx. Handle default output file. Deal with no top module. Automatically run pmuxtree pass. Allow EXTRA_FLAGS and SEED parameters to be set in the environment for tests/tools/autotest.mk. Support FIRRTL regression testing in tests/tools/autotest.sh Add xfirrtl files to test directories to exclude files from FIRRTL regression tests that are known to fail.
* added prefix to FDirection constants, fixing windows buildMiodrag Milanovic2018-09-211-11/+11
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