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| author | Marcelina Kościelnicka <mwk@0x04.net> | 2021-05-22 18:18:50 +0200 |
|---|---|---|
| committer | Marcelina Kościelnicka <mwk@0x04.net> | 2021-05-25 02:07:25 +0200 |
| commit | 69bf5c81c7cf65ccb8bd035eb45137e31a68ae86 (patch) | |
| tree | c27924c314fde30979aa0b91f8b179e71c15dd04 /backends/firrtl | |
| parent | 35ee774ea8eac9b745f93641a192341fe559fa6f (diff) | |
| download | yosys-69bf5c81c7cf65ccb8bd035eb45137e31a68ae86.tar.gz yosys-69bf5c81c7cf65ccb8bd035eb45137e31a68ae86.tar.bz2 yosys-69bf5c81c7cf65ccb8bd035eb45137e31a68ae86.zip | |
Reject wide ports in some passes that will never support them.
Diffstat (limited to 'backends/firrtl')
| -rw-r--r-- | backends/firrtl/firrtl.cc | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/backends/firrtl/firrtl.cc b/backends/firrtl/firrtl.cc index f99becacf..dee24d0e2 100644 --- a/backends/firrtl/firrtl.cc +++ b/backends/firrtl/firrtl.cc @@ -993,6 +993,8 @@ struct FirrtlWorker if (port.clk_enable) log_error("Clocked read port %d on memory %s.%s.\n", i, log_id(module), log_id(mem.memid)); + if (port.wide_log2 != 0) + log_error("Wide read port %d on memory %s.%s. Use memory_narrow to convert them first.\n", i, log_id(module), log_id(mem.memid)); std::ostringstream rpe; @@ -1014,6 +1016,8 @@ struct FirrtlWorker if (!port.clk_enable) log_error("Unclocked write port %d on memory %s.%s.\n", i, log_id(module), log_id(mem.memid)); + if (port.wide_log2 != 0) + log_error("Wide write port %d on memory %s.%s. Use memory_narrow to convert them first.\n", i, log_id(module), log_id(mem.memid)); if (!port.clk_polarity) log_error("Negedge write port %d on memory %s.%s.\n", i, log_id(module), log_id(mem.memid)); for (int i = 1; i < GetSize(port.en); i++) |