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* Use C++11 final/override keywords.whitequark2020-06-181-2/+2
* Improve net priorities in EDIF back-endClaire Wolf2020-04-211-0/+64
* Ignore conflicting keep attributes, unless asked not to. Fixes #1733Claire Wolf2020-04-201-14/+44
* kernel: use more ID::*Eddie Hung2020-04-021-1/+1
* Clean up pseudo-private member usage in `backends/edif/edif.cc`.Alberto Gonzalez2020-04-011-23/+18
* edif: more resilience to mismatched port connection sizes.Marcin Kościelnicki2020-02-061-16/+27
* Preserve wires with keep attribute in EDIF back-endClaire Wolf2020-01-291-9/+34
* Merge pull request #1629 from YosysHQ/mwk/edif-zClaire Wolf2020-01-211-0/+2
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| * edif: Just ignore connections to 'zMarcin Kościelnicki2020-01-131-0/+2
* | remove whitespaceMiodrag Milanovic2020-01-101-1/+1
* | Export wire properties as well in EDIFMiodrag Milanovic2020-01-101-26/+38
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* Add "whitebox" attribute, add "read_verilog -wb"Clifford Wolf2019-04-181-3/+3
* Fix "write_edif -gndvccy"Clifford Wolf2019-03-011-1/+1
* Add "write_edif -gndvccy"Clifford Wolf2019-01-171-5/+13
* Add "write_edif -attrprop"Clifford Wolf2018-10-051-11/+28
* Consistent use of 'override' for virtual methods in derived classes.Henner Zeller2018-07-201-2/+2
* Fix the fixed handling of x-bits in EDIF back-endClifford Wolf2017-07-111-1/+0
* Fix handling of x-bits in EDIF back-endClifford Wolf2017-07-111-1/+11
* Add generation of logic cells to EDIF back-end runtest.pyClifford Wolf2017-03-191-2/+6
* Fix EDIF: portRef member 0 is always the MSB bitClifford Wolf2017-03-192-13/+14
* Add simple EDIF test case generator and checkerClifford Wolf2017-03-181-0/+113
* Improve "write_edif" help messageClifford Wolf2017-02-251-7/+2
* Move EdifNames out of double-private namespaceClifford Wolf2017-02-251-48/+45
* Clean up edif code, swap bit indexing of "upto" portsClifford Wolf2017-02-251-17/+35
* Did as you requested, /but/...Johann Klammer2017-02-241-45/+29
* add options for edif flavorsJohann Klammer2017-02-231-4/+60
* Add warning about x/z bits left unconnected in EDIF outputClifford Wolf2017-02-141-2/+5
* Added "yosys -D" featureClifford Wolf2016-04-211-1/+1
* Fixed some typosClifford Wolf2016-04-051-1/+1
* Added "write_edif -nogndvcc"Clifford Wolf2016-03-081-17/+34
* Fixed trailing whitespacesClifford Wolf2015-07-021-2/+2
* Added EDIF backend support for multi-bit cell portsClifford Wolf2015-02-011-11/+10
* Renamed SIZE() to GetSize() because of name collision on Win32Clifford Wolf2014-10-101-1/+1
* namespace YosysClifford Wolf2014-09-271-0/+4
* Changed backend-api from FILE to std::ostreamClifford Wolf2014-08-231-69/+69
* No implicit conversion from IdString to anything elseClifford Wolf2014-08-021-2/+2
* More cleanups related to RTLIL::IdString usageClifford Wolf2014-08-021-1/+1
* Using log_assert() instead of assert()Clifford Wolf2014-07-281-1/+0
* Refactoring: Renamed RTLIL::Design::modules to modules_Clifford Wolf2014-07-271-6/+6
* Refactoring: Renamed RTLIL::Module::cells to cells_Clifford Wolf2014-07-271-3/+3
* Refactoring: Renamed RTLIL::Module::wires to wires_Clifford Wolf2014-07-271-1/+1
* Changed users of cell->connections_ to the new API (sed command)Clifford Wolf2014-07-261-2/+2
* Renamed RTLIL::{Module,Cell}::connections to connections_Clifford Wolf2014-07-261-2/+2
* Replaced more old SigChunk programming patternsClifford Wolf2014-07-241-9/+6
* Removed RTLIL::SigSpec::optimize()Clifford Wolf2014-07-231-1/+0
* Removed RTLIL::SigSpec::expand() methodClifford Wolf2014-07-231-6/+3
* Refactoring {SigSpec|SigChunk}(RTLIL::Wire *wire, ..) constructor -- step 3/3Clifford Wolf2014-07-231-1/+1
* Refactoring {SigSpec|SigChunk}(RTLIL::Wire *wire, ..) constructor -- step 2/3Clifford Wolf2014-07-231-1/+1
* SigSpec refactoring: using the accessor functions everywhereClifford Wolf2014-07-221-10/+10
* SigSpec refactoring: renamed chunks and width to __chunks and __widthClifford Wolf2014-07-221-10/+10
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