| Commit message (Expand) | Author | Age | Files | Lines |
|---|
| * | Add "whitebox" attribute, add "read_verilog -wb" | Clifford Wolf | 2019-04-18 | 1 | -3/+3 |
| * | Fix "write_edif -gndvccy" | Clifford Wolf | 2019-03-01 | 1 | -1/+1 |
| * | Add "write_edif -gndvccy" | Clifford Wolf | 2019-01-17 | 1 | -5/+13 |
| * | Add "write_edif -attrprop" | Clifford Wolf | 2018-10-05 | 1 | -11/+28 |
| * | Consistent use of 'override' for virtual methods in derived classes. | Henner Zeller | 2018-07-20 | 1 | -2/+2 |
| * | Fix the fixed handling of x-bits in EDIF back-end | Clifford Wolf | 2017-07-11 | 1 | -1/+0 |
| * | Fix handling of x-bits in EDIF back-end | Clifford Wolf | 2017-07-11 | 1 | -1/+11 |
| * | Add generation of logic cells to EDIF back-end runtest.py | Clifford Wolf | 2017-03-19 | 1 | -2/+6 |
| * | Fix EDIF: portRef member 0 is always the MSB bit | Clifford Wolf | 2017-03-19 | 2 | -13/+14 |
| * | Add simple EDIF test case generator and checker | Clifford Wolf | 2017-03-18 | 1 | -0/+113 |
| * | Improve "write_edif" help message | Clifford Wolf | 2017-02-25 | 1 | -7/+2 |
| * | Move EdifNames out of double-private namespace | Clifford Wolf | 2017-02-25 | 1 | -48/+45 |
| * | Clean up edif code, swap bit indexing of "upto" ports | Clifford Wolf | 2017-02-25 | 1 | -17/+35 |
| * | Did as you requested, /but/... | Johann Klammer | 2017-02-24 | 1 | -45/+29 |
| * | add options for edif flavors | Johann Klammer | 2017-02-23 | 1 | -4/+60 |
| * | Add warning about x/z bits left unconnected in EDIF output | Clifford Wolf | 2017-02-14 | 1 | -2/+5 |
| * | Added "yosys -D" feature | Clifford Wolf | 2016-04-21 | 1 | -1/+1 |
| * | Fixed some typos | Clifford Wolf | 2016-04-05 | 1 | -1/+1 |
| * | Added "write_edif -nogndvcc" | Clifford Wolf | 2016-03-08 | 1 | -17/+34 |
| * | Fixed trailing whitespaces | Clifford Wolf | 2015-07-02 | 1 | -2/+2 |
| * | Added EDIF backend support for multi-bit cell ports | Clifford Wolf | 2015-02-01 | 1 | -11/+10 |
| * | Renamed SIZE() to GetSize() because of name collision on Win32 | Clifford Wolf | 2014-10-10 | 1 | -1/+1 |
| * | namespace Yosys | Clifford Wolf | 2014-09-27 | 1 | -0/+4 |
| * | Changed backend-api from FILE to std::ostream | Clifford Wolf | 2014-08-23 | 1 | -69/+69 |
| * | No implicit conversion from IdString to anything else | Clifford Wolf | 2014-08-02 | 1 | -2/+2 |
| * | More cleanups related to RTLIL::IdString usage | Clifford Wolf | 2014-08-02 | 1 | -1/+1 |
| * | Using log_assert() instead of assert() | Clifford Wolf | 2014-07-28 | 1 | -1/+0 |
| * | Refactoring: Renamed RTLIL::Design::modules to modules_ | Clifford Wolf | 2014-07-27 | 1 | -6/+6 |
| * | Refactoring: Renamed RTLIL::Module::cells to cells_ | Clifford Wolf | 2014-07-27 | 1 | -3/+3 |
| * | Refactoring: Renamed RTLIL::Module::wires to wires_ | Clifford Wolf | 2014-07-27 | 1 | -1/+1 |
| * | Changed users of cell->connections_ to the new API (sed command) | Clifford Wolf | 2014-07-26 | 1 | -2/+2 |
| * | Renamed RTLIL::{Module,Cell}::connections to connections_ | Clifford Wolf | 2014-07-26 | 1 | -2/+2 |
| * | Replaced more old SigChunk programming patterns | Clifford Wolf | 2014-07-24 | 1 | -9/+6 |
| * | Removed RTLIL::SigSpec::optimize() | Clifford Wolf | 2014-07-23 | 1 | -1/+0 |
| * | Removed RTLIL::SigSpec::expand() method | Clifford Wolf | 2014-07-23 | 1 | -6/+3 |
| * | Refactoring {SigSpec|SigChunk}(RTLIL::Wire *wire, ..) constructor -- step 3/3 | Clifford Wolf | 2014-07-23 | 1 | -1/+1 |
| * | Refactoring {SigSpec|SigChunk}(RTLIL::Wire *wire, ..) constructor -- step 2/3 | Clifford Wolf | 2014-07-23 | 1 | -1/+1 |
| * | SigSpec refactoring: using the accessor functions everywhere | Clifford Wolf | 2014-07-22 | 1 | -10/+10 |
| * | SigSpec refactoring: renamed chunks and width to __chunks and __width | Clifford Wolf | 2014-07-22 | 1 | -10/+10 |
| * | Better handling of nameDef and nameRef in edif backend | Clifford Wolf | 2014-02-21 | 1 | -21/+27 |
| * | Fixed instantiating multi-bit ports in edif backend | Clifford Wolf | 2014-02-21 | 1 | -2/+4 |
| * | Replaced RTLIL::Const::str with generic decoder method | Clifford Wolf | 2013-12-04 | 1 | -2/+2 |
| * | Added "top" attribute to mark top module in hierarchy | Clifford Wolf | 2013-11-24 | 1 | -0/+5 |
| * | Renamed "placeholder" to "blackbox" | Clifford Wolf | 2013-11-22 | 1 | -3/+3 |
| * | Improved comments on topological sort in edif backend | Clifford Wolf | 2013-11-04 | 1 | -3/+4 |
| * | Added simple topological sort to edif backend | Clifford Wolf | 2013-11-03 | 1 | -2/+30 |
| * | Write yosys version to output files | Clifford Wolf | 2013-11-03 | 1 | -0/+4 |
| * | Fixed hex string generation bug in edif backend | Clifford Wolf | 2013-10-27 | 1 | -4/+4 |
| * | Fixed handling of boolean attributes (backends) | Clifford Wolf | 2013-10-24 | 1 | -3/+3 |
| * | Improvements in EDIF backend | Clifford Wolf | 2013-09-17 | 1 | -1/+40 |
