| Commit message (Expand) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | Add generation of logic cells to EDIF back-end runtest.py | Clifford Wolf | 2017-03-19 | 1 | -2/+6 |
| * | Fix EDIF: portRef member 0 is always the MSB bit | Clifford Wolf | 2017-03-19 | 1 | -7/+11 |
| * | Add simple EDIF test case generator and checker | Clifford Wolf | 2017-03-18 | 1 | -0/+113 |
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index : iCE40/yosys | |
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