| Commit message (Expand) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | write_cxxrtl: enable separate compilation. | whitequark | 2020-04-14 | 1 | -9/+81 |
| * | write_cxxrtl: add basic documentation. | whitequark | 2020-04-09 | 1 | -1/+16 |
| * | write_cxxrtl: add support for $dlatch and $dlatchsr cells. | whitequark | 2020-04-09 | 1 | -3/+16 |
| * | write_cxxrtl: add support for $sr cell. | whitequark | 2020-04-09 | 1 | -27/+35 |
| * | write_cxxrtl: add support for $slice and $concat cells. | whitequark | 2020-04-09 | 1 | -1/+16 |
| * | write_cxxrtl: improve writable memory handling. | whitequark | 2020-04-09 | 2 | -65/+87 |
| * | write_cxxrtl: add support for hierarchical designs. | whitequark | 2020-04-09 | 1 | -18/+107 |
| * | write_cxxrtl: avoid undefined behavior on out-of-bounds memory access. | whitequark | 2020-04-09 | 2 | -46/+78 |
| * | write_cxxrtl: statically schedule comb logic and localize wires. | whitequark | 2020-04-09 | 2 | -68/+368 |
| * | write_cxxrtl: elide wires for results of comb cells used once. | whitequark | 2020-04-09 | 1 | -35/+359 |
| * | write_cxxrtl: new backend. | whitequark | 2020-04-09 | 3 | -0/+2010 |
 |
index : iCE40/yosys | |
| [no description] |
| aboutsummaryrefslogtreecommitdiffstats |