iCE40/yosys - [no description]

	Commit message (Expand)	Author	Age	Files	Lines
*	cxxrtl: add a C API for writing VCD dumps.	whitequark	2020-06-07	1	-0/+2
*	cxxrtl: add a C API for driving and introspecting designs.	whitequark	2020-06-06	1	-29/+46
*	cxxrtl: generate debug information for non-localized public wires.	whitequark	2020-06-06	1	-1/+45
*	cxxrtl: fix implementation of $sshr cell.	whitequark	2020-06-05	1	-1/+1
*	cxxrtl: keep the memory write queue sorted on insertion.	Asu	2020-04-22	1	-3/+5
*	cxxrtl: use one delta cycle for immediately converging netlists.	whitequark	2020-04-21	1	-3/+4
*	cxxrtl: provide attributes to black box factories, too.	whitequark	2020-04-19	1	-10/+10
*	cxxrtl: add simple black box support.	whitequark	2020-04-18	1	-0/+53
*	cxxrtl: make ROMs writable, document memory::operator[].	whitequark	2020-04-16	1	-2/+5
*	write_cxxrtl: improve writable memory handling.	whitequark	2020-04-09	1	-39/+64
*	write_cxxrtl: avoid undefined behavior on out-of-bounds memory access.	whitequark	2020-04-09	1	-8/+13
*	write_cxxrtl: statically schedule comb logic and localize wires.	whitequark	2020-04-09	1	-0/+4
*	write_cxxrtl: new backend.	whitequark	2020-04-09	1	-0/+1104