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* Add support for GHDL modfloor operatorMichael Nolan2022-07-051-0/+21
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* Add $bmux and $demux cells.Marcelina Kościelnicka2022-01-281-0/+36
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* cxxrtl: preserve interior memory pointers across reset.Catherine2021-12-111-21/+3
| | | | | | | | Before this commit, values, wires, and memories with an initializer were value-initialized in emitted C++ code. After this commit, all values, wires, and memories are default-initialized, and the default constructor of generated modules calls the reset() method, which assigns the members that have an initializer.
* cxxrtl: use unique_ptr<value<>[]> to store memory contents.whitequark2021-12-111-16/+16
| | | | This makes the depth properly immutable.
* cxxrtl: add debug_item::{get,set}.whitequark2021-07-181-0/+16
| | | | Fixes #2877.
* cxxrtl: do not use `->template` for non-dependent names.whitequark2021-01-261-8/+8
| | | | This breaks build on MSVC but not GCC/Clang.
* cxxrtl: speed up bit repeats (sign extends, etc).whitequark2020-12-211-0/+8
| | | | | On Minerva SoC SRAM, depending on the compiler, this change improves overall time by 4-7%.
* cxxrtl: disable optimization of debug_items().whitequark2020-12-151-3/+14
| | | | | | | | | | | | | | | | | | Implementing outlining has greatly increased the amount of debug information in a typical build, and consequently exposed performance issues in C++ compilers, which are similar for both GCC and Clang; the compile time of Minerva SoC SRAM increased almost twofold. Although one would expect the slowdown to be caused by the increased use of templates in `debug_eval()`, it is actually almost entirely attributable to optimizations and codegen for `debug_items()`. Fortunately, it is neither possible nor desirable to optimize `debug_items()`: in most cases it is called exactly once, and its body is a linear sequence of calls with unique arguments. This commit turns off optimizations for `debug_items()` on GCC and Clang, improving -Os compile time of Minerva SoC SRAM by ~40% (!)
* cxxrtl: implement debug information outlining.whitequark2020-12-141-5/+36
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Aggressive wire localization and inlining is necessary for CXXRTL to achieve high performance. However, that comes with a cost: reduced debug information coverage. Previously, as a workaround, the `-Og` option could have been used to guarantee complete coverage, at a cost of a significant performance penalty. This commit introduces debug information outlining. The main eval() function is compiled with the user-specified optimization settings. In tandem, an auxiliary debug_eval() function, compiled from the same netlist, can be used to reconstruct the values of localized/inlined signals on demand. To the extent that it is possible, debug_eval() reuses the results of computations performed by eval(), only filling in the missing values. Benchmarking a representative design (Minerva SoC SRAM) shows that: * Switching from `-O4`/`-Og` to `-O6` reduces runtime by ~40%. * Switching from `-g1` to `-g2`, both used with `-O6`, increases compile time by ~25%. * Although `-g2` increases the resident size of generated modules, this has no effect on runtime. Because the impact of `-g2` is minimal and the benefits of having unconditional 100% debug information coverage (and the performance improvement as well) are major, this commit removes `-Og` and changes the defaults to `-O6 -g2`. We'll have our cake and eat it too!
* cxxrtl: don't overwrite buffered inputs.whitequark2020-12-111-1/+1
| | | | | | | | | | | | | | Before this commit, a cell's input was always assigned like: p_cell.p_input = (value...); If `p_input` is buffered (e.g. if the design is built at -O0), this is not correct. (In practice, this breaks clocking.) Unfortunately, the incorrect design was compiled without diagnostics because wire<> was move-assignable and also implicitly constructible from value<>. After this commit, cell inputs are no longer incorrectly assumed to always be unbuffered, and wires are not assignable from values.
* Merge pull request #2468 from whitequark/cxxrtl-assertwhitequark2020-12-021-0/+14
|\ | | | | cxxrtl: use CXXRTL_ASSERT for RTL contract violations instead of assert
| * cxxrtl: use CXXRTL_ASSERT for RTL contract violations instead of assert.whitequark2020-12-021-0/+14
| | | | | | | | | | | | | | | | RTL contract violations and C++ contract violations are different: the former depend on the netlist and will never violate memory safety whereas the latter may. When loading a CXXRTL simulation into another process, RTL contract violations should generally not crash it, while C++ contract violations should.
* | cxxrtl: provide a way to perform unobtrusive power-on reset.whitequark2020-12-021-3/+26
|/ | | | | | | | | | | Although it is always possible to destroy and recreate the design to simulate a power-on reset, this has two drawbacks: * Black boxes are also destroyed and recreated, which causes them to reacquire their resources, which might be costly and/or erase important state. * Pointers into the design are invalidated and have to be acquired again, which is costly and might be very inconvenient if they are captured elsewhere (especially through the C API).
* cxxrtl: expose driver kind in debug information.whitequark2020-09-021-4/+7
| | | | | | This can be useful to determine whether the wire should be a part of a design checkpoint, whether it can be used to override design state, and whether driving it may cause a conflict.
* cxxrtl: expose port direction in debug information.whitequark2020-09-021-4/+18
| | | | | | This can be useful to distinguish e.g. a combinatorially driven wire with type `CXXRTL_VALUE` from a module input with the same type, as well as general introspection.
* cxxrtl.h: Fix incorrect CarryOut in alu()Andy Knowles2020-08-121-8/+3
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* cxxrtl.h: Fix incorrect CarryOut in alu when Bits % 32 != 0 && Invert == FalseAndy Knowles2020-08-121-2/+8
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* cxxrtl: add .get() and .set() accessors on value<> and wire<>.whitequark2020-06-191-6/+47
| | | | | | | | | | | | | For several reasons: * They're more convenient than accessing .data. * They accommodate variably-sized types like size_t transparently. * They statically ensure that no out of range conversions happen. For now these are only provided for unsigned integers, but eventually they should be provided for signed integers too. (Annoyingly this affects conversions to/from `char` at the moment.) Fixes #2127.
* Merge pull request #2159 from MerryMage/cxxrtl-mulwhitequark2020-06-151-17/+22
|\ | | | | cxxrtl: Implement chunk-wise multiplication
| * cxxrtl: Implement chunk-wise multiplicationMerryMage2020-06-151-17/+22
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* | Merge pull request #2158 from miek/sshr-sign-extensionwhitequark2020-06-151-2/+4
|\ \ | |/ |/| cxxrtl: fix sshr sign-extension.
| * cxxrtl: fix sshr sign-extension.Mike Walters2020-06-151-2/+4
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* | Merge pull request #2151 from whitequark/cxxrtl-fix-rzextwhitequark2020-06-131-2/+2
|\ \ | |/ |/| cxxrtl: fix rzext()
| * cxxrtl: fix rzext().whitequark2020-06-131-2/+2
| | | | | | | | | | | | | | This was a correctness issue, but one of the consequences is that it resulted in jumps in generated machine code where there should have been none. As a side effect of fixing the bug, Minerva SoC became 10% faster.
* | Merge pull request #2145 from whitequark/cxxrtl-splitnetswhitequark2020-06-131-37/+80
|\ \ | | | | | | cxxrtl: handle multipart signals
| * | cxxrtl: handle multipart signals.whitequark2020-06-111-1/+32
| | | | | | | | | | | | This avoids losing design visibility when using the `splitnets` pass.
| * | cxxrtl: expose RTLIL::{Wire,Memory}->start_offset in debug info.whitequark2020-06-111-36/+48
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* / cxxrtl: always inline internal cells and slice/concat operations.whitequark2020-06-131-4/+108
|/ | | | | | This can result in massive reduction in runtime, up to 50% depending on workload. Currently people are using `-mllvm -inline-threshold=` as a workaround (with clang++), but this solution is more portable.
* Merge pull request #2141 from whitequark/cxxrtl-cxx11whitequark2020-06-101-5/+6
|\ | | | | cxxrtl: various compiler compatibility fixes
| * cxxrtl: fix a few gcc warnings.whitequark2020-06-101-5/+6
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* | cxxrtl: disambiguate values/wires and their aliases in debug info.whitequark2020-06-101-1/+28
|/ | | | | | | With this change, it is easier to see which signals carry state (only wire<>s appear as `reg` in VCD files) and to construct a minimal checkpoint (CXXRTL_WIRE debug items represent the canonical smallest set of state required to fully reconstruct the simulation).
* cxxrtl: ignore cell input signedness when it is irrelevant.whitequark2020-06-091-57/+19
| | | | | | | | Before this commit, Verilog expressions like `x && 1` would result in references to `logic_and_us` in generated CXXRTL code, which would not compile. After this commit, since cells like that actually behave the same regardless of signedness attributes, the signedness is ignored, which also reduces the template instantiation pressure.
* cxxrtl: emit debug information for constant wires.whitequark2020-06-081-0/+11
| | | | | | | | | Constant wires can represent a significant chunk of the design in generic designs or after optimization. Emitting them in VCD files significantly improves usability because gtkwave removes all traces that are not present in the VCD file after reload, and iterative development suffers if switching a varying signal to a constant disrupts the workflow.
* cxxrtl: add a C API for writing VCD dumps.whitequark2020-06-071-0/+2
| | | | This C API is fully featured.
* cxxrtl: add a C API for driving and introspecting designs.whitequark2020-06-061-29/+46
| | | | | | Compared to the C++ API, the C API currently has two limitations: 1. Memories cannot be updated in a race-free way. 2. Black boxes cannot be implemented in C.
* cxxrtl: generate debug information for non-localized public wires.whitequark2020-06-061-1/+45
| | | | | | | | | | Debug information describes values, wires, and memories with a simple C-compatible layout. It can be emitted on demand into a map, which has no runtime cost when it is unused, and allows late bound designs. The `hdlname` attribute is used as the lookup key such that original names, as emitted by the frontend, can be used for debugging and introspection.
* cxxrtl: fix implementation of $sshr cell.whitequark2020-06-051-1/+1
| | | | Fixes #2111.
* cxxrtl: keep the memory write queue sorted on insertion.Asu2020-04-221-3/+5
| | | | | | | Strategically inserting the pending memory write in memory::update to keep the queue sorted allows us to skip the queue sort in memory::commit. The Minerva SRAM SoC runs ~7% faster as a result.
* cxxrtl: use one delta cycle for immediately converging netlists.whitequark2020-04-211-3/+4
| | | | | | | | | | | If it is statically known that eval() will converge in one delta cycle (that is, the second commit() will always return `false`) because the design contains no feedback or buffered wires, then there is no need to run the second delta cycle at all. After this commit, the case where eval() always converges immediately is detected and the second delta cycle is omitted. As a result, Minerva SRAM SoC runs ~25% faster.
* cxxrtl: provide attributes to black box factories, too.whitequark2020-04-191-10/+10
| | | | | | | | | Both parameters and attributes are necessary because the parameters have to be the same between every instantiation of the cell, but attributes may well vary. For example, for an UART PHY, the type of the PHY (tty, pty, socket) would be a parameter, but configuration of the implementation specified by the type (socket address) would be an attribute.
* cxxrtl: add simple black box support.whitequark2020-04-181-0/+53
| | | | | | | This commit adds support for replacing RTLIL modules with CXXRTL black boxes. Black box port widths may not depend on the parameters with which it is instantiated (yet); the parameters may only be used to change the behavior of the black box.
* cxxrtl: make ROMs writable, document memory::operator[].whitequark2020-04-161-2/+5
| | | | | | | | | | | There is no practical benefit from using `const memory` for ROMs; it uses an std::vector internally, which prevents contemporary compilers from constant-propagating ROM contents. (It is not clear whether they are permitted to do so.) However, there is a major benefit from using non-const `memory` for ROMs, which is the ability to dynamically fill the ROM for each individual simulation.
* write_cxxrtl: improve writable memory handling.whitequark2020-04-091-39/+64
| | | | | | This commit reduces space and time overhead for writable memories to O(write port count) in both cases; implements handling for write port priorities; and simplifies runtime representation of memories.
* write_cxxrtl: avoid undefined behavior on out-of-bounds memory access.whitequark2020-04-091-8/+13
| | | | | | | | | | After this commit, if NDEBUG is not defined, out-of-bounds accesses cause assertion failures for reads and writes. If NDEBUG is defined, out-of-bounds reads return zeroes, and out-of-bounds writes are ignored. This commit also adds support for memories that start with a non-zero index (`Memory::start_offset` in RTLIL).
* write_cxxrtl: statically schedule comb logic and localize wires.whitequark2020-04-091-0/+4
| | | | | | This results in further massive gains in performance, modest decrease in compile time, and, for designs without feedback arcs, makes it possible to run eval() once per clock edge in certain conditions.
* write_cxxrtl: new backend.whitequark2020-04-091-0/+1104
This commit adds a basic implementation that isn't very performant but implements most of the planned features.
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